| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC |
| 4 | * |
| 5 | * Baikal-T1 CCU clock indices |
| 6 | */ |
| 7 | #ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H |
| 8 | #define __DT_BINDINGS_CLOCK_BT1_CCU_H |
| 9 | |
| 10 | #define CCU_CPU_PLL 0 |
| 11 | #define CCU_SATA_PLL 1 |
| 12 | #define CCU_DDR_PLL 2 |
| 13 | #define CCU_PCIE_PLL 3 |
| 14 | #define CCU_ETH_PLL 4 |
| 15 | |
| 16 | #define CCU_AXI_MAIN_CLK 0 |
| 17 | #define CCU_AXI_DDR_CLK 1 |
| 18 | #define CCU_AXI_SATA_CLK 2 |
| 19 | #define CCU_AXI_GMAC0_CLK 3 |
| 20 | #define CCU_AXI_GMAC1_CLK 4 |
| 21 | #define CCU_AXI_XGMAC_CLK 5 |
| 22 | #define CCU_AXI_PCIE_M_CLK 6 |
| 23 | #define CCU_AXI_PCIE_S_CLK 7 |
| 24 | #define CCU_AXI_USB_CLK 8 |
| 25 | #define CCU_AXI_HWA_CLK 9 |
| 26 | #define CCU_AXI_SRAM_CLK 10 |
| 27 | |
| 28 | #define CCU_SYS_SATA_REF_CLK 0 |
| 29 | #define CCU_SYS_APB_CLK 1 |
| 30 | #define CCU_SYS_GMAC0_TX_CLK 2 |
| 31 | #define CCU_SYS_GMAC0_PTP_CLK 3 |
| 32 | #define CCU_SYS_GMAC1_TX_CLK 4 |
| 33 | #define CCU_SYS_GMAC1_PTP_CLK 5 |
| 34 | #define CCU_SYS_XGMAC_REF_CLK 6 |
| 35 | #define CCU_SYS_XGMAC_PTP_CLK 7 |
| 36 | #define CCU_SYS_USB_CLK 8 |
| 37 | #define CCU_SYS_PVT_CLK 9 |
| 38 | #define CCU_SYS_HWA_CLK 10 |
| 39 | #define CCU_SYS_UART_CLK 11 |
| 40 | #define CCU_SYS_I2C1_CLK 12 |
| 41 | #define CCU_SYS_I2C2_CLK 13 |
| 42 | #define CCU_SYS_GPIO_CLK 14 |
| 43 | #define CCU_SYS_TIMER0_CLK 15 |
| 44 | #define CCU_SYS_TIMER1_CLK 16 |
| 45 | #define CCU_SYS_TIMER2_CLK 17 |
| 46 | #define CCU_SYS_WDT_CLK 18 |
| 47 | |
| 48 | #endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ |