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git01.mediatek.com / filogic / uboot / 94ef0166f2cd373ee29a9bb11cb8150561750139 / . / dts / upstream / Bindings / mmc / renesas,sdhi.yaml
blob: 29f2400247ebc6746e92ed8ad1f7ebb2129a3e03 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas SDHI SD/MMC controller
8
9maintainers:
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
11
12properties:
13 compatible:
14 oneOf:
15 - items:
16 - const: renesas,sdhi-sh73a0 # R-Mobile APE6
17 - items:
18 - const: renesas,sdhi-r7s72100 # RZ/A1H
19 - items:
20 - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
21 - items:
22 - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
23 - items:
24 - const: renesas,sdhi-r8a7740 # R-Mobile A1
25 - items:
26 - enum:
27 - renesas,sdhi-r8a7778 # R-Car M1
28 - renesas,sdhi-r8a7779 # R-Car H1
29 - const: renesas,rcar-gen1-sdhi # R-Car Gen1
30 - items:
31 - enum:
32 - renesas,sdhi-r8a7742 # RZ/G1H
33 - renesas,sdhi-r8a7743 # RZ/G1M
34 - renesas,sdhi-r8a7744 # RZ/G1N
35 - renesas,sdhi-r8a7745 # RZ/G1E
36 - renesas,sdhi-r8a77470 # RZ/G1C
37 - renesas,sdhi-r8a7790 # R-Car H2
38 - renesas,sdhi-r8a7791 # R-Car M2-W
39 - renesas,sdhi-r8a7792 # R-Car V2H
40 - renesas,sdhi-r8a7793 # R-Car M2-N
41 - renesas,sdhi-r8a7794 # R-Car E2
42 - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
43 - items:
44 - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
45 - items:
46 - enum:
47 - renesas,sdhi-r8a774a1 # RZ/G2M
48 - renesas,sdhi-r8a774b1 # RZ/G2N
49 - renesas,sdhi-r8a774c0 # RZ/G2E
50 - renesas,sdhi-r8a774e1 # RZ/G2H
51 - renesas,sdhi-r8a7795 # R-Car H3
52 - renesas,sdhi-r8a7796 # R-Car M3-W
53 - renesas,sdhi-r8a77961 # R-Car M3-W+
54 - renesas,sdhi-r8a77965 # R-Car M3-N
55 - renesas,sdhi-r8a77970 # R-Car V3M
56 - renesas,sdhi-r8a77980 # R-Car V3H
57 - renesas,sdhi-r8a77990 # R-Car E3
58 - renesas,sdhi-r8a77995 # R-Car D3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]59 - renesas,sdhi-r9a07g043 # RZ/G2UL and RZ/Five
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]60 - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
61 - renesas,sdhi-r9a07g054 # RZ/V2L
62 - renesas,sdhi-r9a08g045 # RZ/G3S
63 - renesas,sdhi-r9a09g011 # RZ/V2M
64 - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
65 - items:
66 - enum:
67 - renesas,sdhi-r8a779a0 # R-Car V3U
68 - renesas,sdhi-r8a779f0 # R-Car S4-8
69 - renesas,sdhi-r8a779g0 # R-Car V4H
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]70 - renesas,sdhi-r8a779h0 # R-Car V4M
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]71 - const: renesas,rcar-gen4-sdhi # R-Car Gen4
72
73 reg:
74 maxItems: 1
75
76 interrupts:
77 minItems: 1
78 maxItems: 3
79
80 clocks: true
81
82 clock-names: true
83
84 dmas:
85 minItems: 4
86 maxItems: 4
87
88 dma-names:
89 minItems: 4
90 maxItems: 4
91 items:
92 enum:
93 - tx
94 - rx
95
96 iommus:
97 maxItems: 1
98
99 power-domains:
100 maxItems: 1
101
102 resets:
103 maxItems: 1
104
105 pinctrl-0:
106 minItems: 1
107 maxItems: 2
108
109 pinctrl-1:
110 maxItems: 1
111
112 pinctrl-names: true
113
114 max-frequency: true
115
116allOf:
117 - $ref: mmc-controller.yaml
118
119 - if:
120 properties:
121 compatible:
122 contains:
123 enum:
124 - renesas,sdhi-r9a07g043
125 - renesas,sdhi-r9a07g044
126 - renesas,sdhi-r9a07g054
127 - renesas,sdhi-r9a08g045
128 - renesas,sdhi-r9a09g011
129 then:
130 properties:
131 clocks:
132 items:
133 - description: IMCLK, SDHI channel main clock1.
134 - description: CLK_HS, SDHI channel High speed clock which operates
135 4 times that of SDHI channel main clock1.
136 - description: IMCLK2, SDHI channel main clock2. When this clock is
137 turned off, external SD card detection cannot be
138 detected.
139 - description: ACLK, SDHI channel bus clock.
140 clock-names:
141 items:
142 - const: core
143 - const: clkh
144 - const: cd
145 - const: aclk
146 required:
147 - clock-names
148 - resets
149 else:
150 if:
151 properties:
152 compatible:
153 contains:
154 enum:
155 - renesas,rcar-gen2-sdhi
156 - renesas,rcar-gen3-sdhi
157 - renesas,rcar-gen4-sdhi
158 then:
159 properties:
160 clocks:
161 minItems: 1
162 maxItems: 3
163 clock-names:
164 minItems: 1
165 uniqueItems: true
166 items:
167 - const: core
168 - enum: [ clkh, cd ]
169 - const: cd
170 else:
171 properties:
172 clocks:
173 minItems: 1
174 maxItems: 2
175 clock-names:
176 minItems: 1
177 items:
178 - const: core
179 - const: cd
180
181 - if:
182 properties:
183 compatible:
184 contains:
185 const: renesas,sdhi-mmc-r8a77470
186 then:
187 properties:
188 pinctrl-names:
189 items:
190 - const: state_uhs
191 else:
192 properties:
193 pinctrl-names:
194 minItems: 1
195 items:
196 - const: default
197 - const: state_uhs
198
199 - if:
200 properties:
201 compatible:
202 contains:
203 enum:
204 - renesas,sdhi-r7s72100
205 - renesas,sdhi-r7s9210
206 then:
207 required:
208 - clock-names
209 description:
210 The internal card detection logic that exists in these controllers is
211 sectioned off to be run by a separate second clock source to allow
212 the main core clock to be turned off to save power.
213
214required:
215 - compatible
216 - reg
217 - interrupts
218 - clocks
219 - power-domains
220
221unevaluatedProperties: false
222
223examples:
224 - |
225 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
226 #include <dt-bindings/interrupt-controller/arm-gic.h>
227 #include <dt-bindings/power/r8a7790-sysc.h>
228
229 sdhi0: mmc@ee100000 {
230 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
231 reg = <0xee100000 0x328>;
232 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cpg CPG_MOD 314>;
234 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
235 dma-names = "tx", "rx", "tx", "rx";
236 max-frequency = <195000000>;
237 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
238 resets = <&cpg 314>;
239 };
240
241 sdhi1: mmc@ee120000 {
242 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
243 reg = <0xee120000 0x328>;
244 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cpg CPG_MOD 313>;
246 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
247 dma-names = "tx", "rx", "tx", "rx";
248 max-frequency = <195000000>;
249 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
250 resets = <&cpg 313>;
251 };
252
253 sdhi2: mmc@ee140000 {
254 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
255 reg = <0xee140000 0x100>;
256 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cpg CPG_MOD 312>;
258 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
259 dma-names = "tx", "rx", "tx", "rx";
260 max-frequency = <97500000>;
261 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
262 resets = <&cpg 312>;
263 };
264
265 sdhi3: mmc@ee160000 {
266 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
267 reg = <0xee160000 0x100>;
268 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cpg CPG_MOD 311>;
270 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
271 dma-names = "tx", "rx", "tx", "rx";
272 max-frequency = <97500000>;
273 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
274 resets = <&cpg 311>;
275 };