dts/upstream/Bindings/display/msm/qcom,x1e80100-mdss.yaml

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm X1E80100 Display MDSS

maintainers:
  - Abel Vesa <abel.vesa@linaro.org>

description:
  X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
  DPU display controller, DP interfaces, etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,x1e80100-mdss

  clocks:
    items:
      - description: Display AHB
      - description: Display hf AXI
      - description: Display core

  iommus:
    maxItems: 1

  interconnects:
    maxItems: 3

  interconnect-names:
    maxItems: 3

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,x1e80100-dpu

  "^displayport-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,x1e80100-dp

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true
    properties:
      compatible:
        const: qcom,x1e80100-dp-phy

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
    #include <dt-bindings/phy/phy-qcom-qmp.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>

    display-subsystem@ae00000 {
        compatible = "qcom,x1e80100-mdss";
        reg = <0x0ae00000 0x1000>;
        reg-names = "mdss";

        interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
                        <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
        interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";

        resets = <&dispcc_core_bcr>;

        power-domains = <&dispcc_gdsc>;

        clocks = <&dispcc_ahb_clk>,
                 <&gcc_disp_hf_axi_clk>,
                 <&dispcc_mdp_clk>;
        clock-names = "bus", "nrt_bus", "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x1c00 0x2>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@ae01000 {
            compatible = "qcom,x1e80100-dpu";
            reg = <0x0ae01000 0x8f000>,
                  <0x0aeb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc_axi_clk>,
                     <&dispcc_ahb_clk>,
                     <&dispcc_mdp_lut_clk>,
                     <&dispcc_mdp_clk>,
                     <&dispcc_mdp_vsync_clk>;
            clock-names = "nrt_bus",
                          "iface",
                          "lut",
                          "core",
                          "vsync";

            assigned-clocks = <&dispcc_mdp_vsync_clk>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmhpd RPMHPD_MMCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dpu_intf2_out: endpoint {
                        remote-endpoint = <&dsi1_in>;
                    };
                };
            };

            mdp_opp_table: opp-table {
                compatible = "operating-points-v2";

                opp-200000000 {
                    opp-hz = /bits/ 64 <200000000>;
                    required-opps = <&rpmhpd_opp_low_svs>;
                };

                opp-325000000 {
                    opp-hz = /bits/ 64 <325000000>;
                    required-opps = <&rpmhpd_opp_svs>;
                };

                opp-375000000 {
                    opp-hz = /bits/ 64 <375000000>;
                    required-opps = <&rpmhpd_opp_svs_l1>;
                };

                opp-514000000 {
                    opp-hz = /bits/ 64 <514000000>;
                    required-opps = <&rpmhpd_opp_nom>;
                };
            };
        };

        displayport-controller@ae90000 {
            compatible = "qcom,x1e80100-dp";
            reg = <0 0xae90000 0 0x200>,
                  <0 0xae90200 0 0x200>,
                  <0 0xae90400 0 0x600>,
                  <0 0xae91000 0 0x400>,
                  <0 0xae91400 0 0x400>;

            interrupt-parent = <&mdss>;
            interrupts = <12>;

            clocks = <&dispcc_mdss_ahb_clk>,
               <&dispcc_dptx0_aux_clk>,
               <&dispcc_dptx0_link_clk>,
               <&dispcc_dptx0_link_intf_clk>,
               <&dispcc_dptx0_pixel0_clk>;
            clock-names = "core_iface", "core_aux",
                    "ctrl_link",
                    "ctrl_link_iface",
                    "stream_pixel";

            assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,
                  <&dispcc_mdss_dptx0_pixel0_clk_src>;
            assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
                  <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

            operating-points-v2 = <&mdss_dp0_opp_table>;

            power-domains = <&rpmhpd RPMHPD_MMCX>;

            phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
            phy-names = "dp";

            #sound-dai-cells = <0>;

            ports {
              #address-cells = <1>;
              #size-cells = <0>;

              port@0 {
                  reg = <0>;

                  mdss_dp0_in: endpoint {
                    remote-endpoint = <&mdss_intf0_out>;
                  };
              };

              port@1 {
                  reg = <1>;

                  mdss_dp0_out: endpoint {
                  };
              };
            };

            mdss_dp0_opp_table: opp-table {
              compatible = "operating-points-v2";

              opp-160000000 {
                 opp-hz = /bits/ 64 <160000000>;
                 required-opps = <&rpmhpd_opp_low_svs>;
              };

              opp-270000000 {
                 opp-hz = /bits/ 64 <270000000>;
                 required-opps = <&rpmhpd_opp_svs>;
              };

              opp-540000000 {
                 opp-hz = /bits/ 64 <540000000>;
                 required-opps = <&rpmhpd_opp_svs_l1>;
              };

              opp-810000000 {
                 opp-hz = /bits/ 64 <810000000>;
                 required-opps = <&rpmhpd_opp_nom>;
              };
            };
        };
    };
...