blob: 3028957953bdaff2d7feef10f1082b27d69154ad [file] [log] [blame]
Giulio Benetti9dba2622020-01-10 15:51:47 +01001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
Simon Glass97589732020-05-10 11:40:02 -06007#include <init.h>
Giulio Benetti9dba2622020-01-10 15:51:47 +01008#include <asm/io.h>
9#include <asm/armv7_mpu.h>
Giulio Benetti3d1a5732021-05-20 16:10:13 +020010#include <asm/mach-imx/sys_proto.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060011#include <linux/bitops.h>
Giulio Benetti9dba2622020-01-10 15:51:47 +010012
13int arch_cpu_init(void)
14{
15 int i;
16
Giulio Benetti86c4dc32021-05-13 12:18:30 +020017 struct mpu_region_config imxrt_region_config[] = {
Giulio Benetti9dba2622020-01-10 15:51:47 +010018 { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
19 STRONG_ORDER, REGION_4GB },
20 { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW,
21 O_I_WB_RD_WR_ALLOC, (ffs(PHYS_SDRAM_SIZE) - 2) },
22 { DMAMEM_BASE,
23 REGION_2, XN_DIS, PRIV_RW_USR_RW,
24 STRONG_ORDER, (ffs(DMAMEM_SZ_ALL) - 2) },
25 };
26
27 /*
28 * Configure the memory protection unit (MPU) to allow full access to
29 * the whole 4GB address space.
30 */
31 disable_mpu();
Giulio Benetti86c4dc32021-05-13 12:18:30 +020032 for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++)
33 mpu_config(&imxrt_region_config[i]);
Giulio Benetti9dba2622020-01-10 15:51:47 +010034 enable_mpu();
35
36 return 0;
37}
Giulio Benetti3d1a5732021-05-20 16:10:13 +020038
39u32 get_cpu_rev(void)
40{
41#if defined(CONFIG_IMXRT1020)
42 return MXC_CPU_IMXRT1020 << 12;
43#elif defined(CONFIG_IMXRT1050)
44 return MXC_CPU_IMXRT1050 << 12;
Jesse Taube9451ffe2022-07-26 01:43:39 -040045#elif defined(CONFIG_IMXRT1170)
46 return MXC_CPU_IMXRT1170 << 12;
Giulio Benetti3d1a5732021-05-20 16:10:13 +020047#else
48#error This IMXRT SoC is not supported
49#endif
50}