Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017 |
| 3 | * Patrice Chotard <patrice.chotard@st.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0 |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <dm.h> |
| 10 | #include <mmc.h> |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 11 | #include <reset-uclass.h> |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 12 | #include <sdhci.h> |
| 13 | #include <asm/arch/sdhci.h> |
| 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | struct sti_sdhci_plat { |
| 18 | struct mmc_config cfg; |
| 19 | struct mmc mmc; |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 20 | struct reset_ctl reset; |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 21 | int instance; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 22 | }; |
| 23 | |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 24 | /** |
| 25 | * sti_mmc_core_config: configure the Arasan HC |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 26 | * @dev : udevice |
| 27 | * |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 28 | * Description: this function is to configure the Arasan MMC HC. |
| 29 | * This should be called when the system starts in case of, on the SoC, |
| 30 | * it is needed to configure the host controller. |
| 31 | * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS |
| 32 | * needs to be configured as MMC 4.5 to have full capabilities. |
| 33 | * W/o these settings the SDHCI could configure and use the embedded controller |
| 34 | * with limited features. |
| 35 | */ |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 36 | static int sti_mmc_core_config(struct udevice *dev) |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 37 | { |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 38 | struct sti_sdhci_plat *plat = dev_get_platdata(dev); |
| 39 | struct sdhci_host *host = dev_get_priv(dev); |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 40 | int ret; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 41 | |
| 42 | /* only MMC1 has a reset line */ |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 43 | if (plat->instance) { |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 44 | ret = reset_deassert(&plat->reset); |
| 45 | if (ret < 0) { |
| 46 | error("MMC1 deassert failed: %d", ret); |
| 47 | return ret; |
| 48 | } |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | writel(STI_FLASHSS_MMC_CORE_CONFIG_1, |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 52 | host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1); |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 53 | |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 54 | if (plat->instance) { |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 55 | writel(STI_FLASHSS_MMC_CORE_CONFIG2, |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 56 | host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2); |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 57 | writel(STI_FLASHSS_MMC_CORE_CONFIG3, |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 58 | host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3); |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 59 | } else { |
| 60 | writel(STI_FLASHSS_SDCARD_CORE_CONFIG2, |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 61 | host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2); |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 62 | writel(STI_FLASHSS_SDCARD_CORE_CONFIG3, |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 63 | host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3); |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 64 | } |
| 65 | writel(STI_FLASHSS_MMC_CORE_CONFIG4, |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 66 | host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4); |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 67 | |
| 68 | return 0; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | static int sti_sdhci_probe(struct udevice *dev) |
| 72 | { |
| 73 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
| 74 | struct sti_sdhci_plat *plat = dev_get_platdata(dev); |
| 75 | struct sdhci_host *host = dev_get_priv(dev); |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 76 | int ret; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * identify current mmc instance, mmc1 has a reset, not mmc0 |
| 80 | * MMC0 is wired to the SD slot, |
| 81 | * MMC1 is wired on the high speed connector |
| 82 | */ |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 83 | ret = reset_get_by_index(dev, 0, &plat->reset); |
| 84 | if (!ret) |
Patrice Chotard | 1b888b8 | 2017-09-05 11:04:18 +0200 | [diff] [blame] | 85 | plat->instance = 1; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 86 | else |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 87 | if (ret == -ENOENT) |
| 88 | plat->instance = 0; |
| 89 | else |
| 90 | return ret; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 91 | |
Patrice Chotard | 36904ad | 2017-09-05 11:04:20 +0200 | [diff] [blame] | 92 | ret = sti_mmc_core_config(dev); |
| 93 | if (ret) |
| 94 | return ret; |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 95 | |
| 96 | host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | |
| 97 | SDHCI_QUIRK_32BIT_DMA_ADDR | |
| 98 | SDHCI_QUIRK_NO_HISPD_BIT; |
| 99 | |
| 100 | host->host_caps = MMC_MODE_DDR_52MHz; |
| 101 | |
| 102 | ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000); |
| 103 | if (ret) |
| 104 | return ret; |
| 105 | |
| 106 | host->mmc = &plat->mmc; |
| 107 | host->mmc->priv = host; |
| 108 | host->mmc->dev = dev; |
| 109 | upriv->mmc = host->mmc; |
| 110 | |
| 111 | return sdhci_probe(dev); |
| 112 | } |
| 113 | |
| 114 | static int sti_sdhci_ofdata_to_platdata(struct udevice *dev) |
| 115 | { |
| 116 | struct sdhci_host *host = dev_get_priv(dev); |
| 117 | |
| 118 | host->name = strdup(dev->name); |
Simon Glass | ba1dea4 | 2017-05-17 17:18:05 -0600 | [diff] [blame] | 119 | host->ioaddr = (void *)devfdt_get_addr(dev); |
Patrice Chotard | 2eea7d8 | 2017-02-21 13:37:09 +0100 | [diff] [blame] | 120 | |
| 121 | host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
| 122 | "bus-width", 4); |
| 123 | |
| 124 | return 0; |
| 125 | } |
| 126 | |
| 127 | static int sti_sdhci_bind(struct udevice *dev) |
| 128 | { |
| 129 | struct sti_sdhci_plat *plat = dev_get_platdata(dev); |
| 130 | |
| 131 | return sdhci_bind(dev, &plat->mmc, &plat->cfg); |
| 132 | } |
| 133 | |
| 134 | static const struct udevice_id sti_sdhci_ids[] = { |
| 135 | { .compatible = "st,sdhci" }, |
| 136 | { } |
| 137 | }; |
| 138 | |
| 139 | U_BOOT_DRIVER(sti_mmc) = { |
| 140 | .name = "sti_sdhci", |
| 141 | .id = UCLASS_MMC, |
| 142 | .of_match = sti_sdhci_ids, |
| 143 | .bind = sti_sdhci_bind, |
| 144 | .ops = &sdhci_ops, |
| 145 | .ofdata_to_platdata = sti_sdhci_ofdata_to_platdata, |
| 146 | .probe = sti_sdhci_probe, |
| 147 | .priv_auto_alloc_size = sizeof(struct sdhci_host), |
| 148 | .platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat), |
| 149 | }; |