Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
| 7 | * |
| 8 | * (C) Copyright 2006 |
| 9 | * Eric Schumann, Phytec Messtechnik GmbH |
| 10 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 11 | * SPDX-License-Identifier: GPL-2.0+ |
Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <common.h> |
| 15 | #include <mpc5xxx.h> |
| 16 | #include <pci.h> |
Peter Tyser | 133c0fe | 2010-04-12 22:28:07 -0500 | [diff] [blame] | 17 | #include <asm/io.h> |
Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 18 | |
| 19 | #include "mt46v32m16-75.h" |
| 20 | |
| 21 | #ifndef CONFIG_SYS_RAMBOOT |
| 22 | static void sdram_start(int hi_addr) |
| 23 | { |
| 24 | volatile struct mpc5xxx_cdm *cdm = |
| 25 | (struct mpc5xxx_cdm *)MPC5XXX_CDM; |
| 26 | volatile struct mpc5xxx_sdram *sdram = |
| 27 | (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; |
| 28 | |
| 29 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
| 30 | |
| 31 | /* unlock mode register */ |
| 32 | out_be32 (&sdram->ctrl, |
| 33 | (SDRAM_CONTROL | 0x80000000 | hi_addr_bit)); |
| 34 | |
| 35 | /* precharge all banks */ |
| 36 | out_be32 (&sdram->ctrl, |
| 37 | (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); |
| 38 | |
| 39 | #ifdef SDRAM_DDR |
| 40 | /* set mode register: extended mode */ |
| 41 | out_be32 (&sdram->mode, (SDRAM_EMODE)); |
| 42 | |
| 43 | /* set mode register: reset DLL */ |
| 44 | out_be32 (&sdram->mode, |
| 45 | (SDRAM_MODE | 0x04000000)); |
| 46 | #endif |
| 47 | |
| 48 | /* precharge all banks */ |
| 49 | out_be32 (&sdram->ctrl, |
| 50 | (SDRAM_CONTROL | 0x80000002 | hi_addr_bit)); |
| 51 | |
| 52 | /* auto refresh */ |
| 53 | out_be32 (&sdram->ctrl, |
| 54 | (SDRAM_CONTROL | 0x80000004 | hi_addr_bit)); |
| 55 | |
| 56 | /* set mode register */ |
| 57 | out_be32 (&sdram->mode, (SDRAM_MODE)); |
| 58 | |
| 59 | /* normal operation */ |
| 60 | out_be32 (&sdram->ctrl, |
| 61 | (SDRAM_CONTROL | hi_addr_bit)); |
| 62 | |
| 63 | /* set CDM clock enable register, set MPC5200B SDRAM bus */ |
| 64 | /* to reduced driver strength */ |
| 65 | out_be32 (&cdm->clock_enable, (0x00CFFFFF)); |
| 66 | } |
| 67 | #endif |
| 68 | |
| 69 | /* |
| 70 | * ATTENTION: Although partially referenced initdram does NOT make |
| 71 | * real use of CONFIG_SYS_SDRAM_BASE. The code does not |
| 72 | * work if CONFIG_SYS_SDRAM_BASE |
| 73 | * is something else than 0x00000000. |
| 74 | */ |
| 75 | |
| 76 | phys_size_t initdram(int board_type) |
| 77 | { |
| 78 | volatile struct mpc5xxx_mmap_ctl *mm = |
| 79 | (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; |
| 80 | volatile struct mpc5xxx_cdm *cdm = |
| 81 | (struct mpc5xxx_cdm *)MPC5XXX_CDM; |
| 82 | volatile struct mpc5xxx_sdram *sdram = |
| 83 | (struct mpc5xxx_sdram *)MPC5XXX_SDRAM; |
| 84 | ulong dramsize = 0; |
| 85 | ulong dramsize2 = 0; |
| 86 | #ifndef CONFIG_SYS_RAMBOOT |
| 87 | ulong test1, test2; |
| 88 | |
| 89 | /* setup SDRAM chip selects */ |
| 90 | /* 256MB at 0x0 */ |
| 91 | out_be32 (&mm->sdram0, 0x0000001b); |
| 92 | /* disabled */ |
| 93 | out_be32 (&mm->sdram1, 0x10000000); |
| 94 | |
| 95 | /* setup config registers */ |
| 96 | out_be32 (&sdram->config1, SDRAM_CONFIG1); |
| 97 | out_be32 (&sdram->config2, SDRAM_CONFIG2); |
| 98 | |
| 99 | #if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY) |
| 100 | /* set tap delay */ |
| 101 | out_be32 (&cdm->porcfg, SDRAM_TAPDELAY); |
| 102 | #endif |
| 103 | |
| 104 | /* find RAM size using SDRAM CS0 only */ |
| 105 | sdram_start(0); |
| 106 | test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); |
| 107 | sdram_start(1); |
| 108 | test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000); |
| 109 | if (test1 > test2) { |
| 110 | sdram_start(0); |
| 111 | dramsize = test1; |
| 112 | } else |
| 113 | dramsize = test2; |
| 114 | |
| 115 | /* memory smaller than 1MB is impossible */ |
| 116 | if (dramsize < (1 << 20)) |
| 117 | dramsize = 0; |
| 118 | |
| 119 | /* set SDRAM CS0 size according to the amount of RAM found */ |
| 120 | if (dramsize > 0) { |
| 121 | out_be32 (&mm->sdram0, |
| 122 | (0x13 + __builtin_ffs(dramsize >> 20) - 1)); |
| 123 | } else { |
| 124 | /* disabled */ |
| 125 | out_be32 (&mm->sdram0, 0); |
| 126 | } |
| 127 | |
| 128 | #else /* CONFIG_SYS_RAMBOOT */ |
| 129 | |
| 130 | /* retrieve size of memory connected to SDRAM CS0 */ |
| 131 | dramsize = in_be32(&mm->sdram0) & 0xFF; |
| 132 | if (dramsize >= 0x13) |
| 133 | dramsize = (1 << (dramsize - 0x13)) << 20; |
| 134 | else |
| 135 | dramsize = 0; |
| 136 | |
| 137 | /* retrieve size of memory connected to SDRAM CS1 */ |
| 138 | dramsize2 = in_be32(&mm->sdram1) & 0xFF; |
| 139 | if (dramsize2 >= 0x13) |
| 140 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
| 141 | else |
| 142 | dramsize2 = 0; |
| 143 | |
| 144 | #endif /* CONFIG_SYS_RAMBOOT */ |
| 145 | |
| 146 | return dramsize + dramsize2; |
| 147 | } |
| 148 | |
| 149 | int checkboard(void) |
| 150 | { |
| 151 | puts("Board: phyCORE-MPC5200B-tiny\n"); |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | #ifdef CONFIG_PCI |
| 156 | static struct pci_controller hose; |
| 157 | |
| 158 | extern void pci_mpc5xxx_init(struct pci_controller *); |
| 159 | |
| 160 | void pci_init_board(void) |
| 161 | { |
| 162 | pci_mpc5xxx_init(&hose); |
| 163 | } |
| 164 | #endif |
| 165 | |
Robert P. J. Day | 3c75700 | 2016-05-19 15:23:12 -0400 | [diff] [blame] | 166 | #ifdef CONFIG_OF_BOARD_SETUP |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 167 | int ft_board_setup(void *blob, bd_t *bd) |
Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 168 | { |
| 169 | ft_cpu_setup(blob, bd); |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 170 | |
| 171 | return 0; |
Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 172 | } |
Robert P. J. Day | 3c75700 | 2016-05-19 15:23:12 -0400 | [diff] [blame] | 173 | #endif /* CONFIG_OF_BOARD_SETUP */ |
Jon Smirl | bc03df9 | 2009-06-14 18:21:28 -0400 | [diff] [blame] | 174 | |
| 175 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
| 176 | |
| 177 | #define GPIO_PSC2_4 0x02000000UL |
| 178 | |
| 179 | void init_ide_reset(void) |
| 180 | { |
| 181 | volatile struct mpc5xxx_wu_gpio *wu_gpio = |
| 182 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; |
| 183 | debug("init_ide_reset\n"); |
| 184 | |
| 185 | /* Configure PSC2_4 as GPIO output for ATA reset */ |
| 186 | setbits_be32(&wu_gpio->enable, GPIO_PSC2_4); |
| 187 | setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4); |
| 188 | /* Deassert reset */ |
| 189 | setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); |
| 190 | } |
| 191 | |
| 192 | void ide_set_reset(int idereset) |
| 193 | { |
| 194 | volatile struct mpc5xxx_wu_gpio *wu_gpio = |
| 195 | (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO; |
| 196 | debug("ide_reset(%d)\n", idereset); |
| 197 | |
| 198 | if (idereset) { |
| 199 | clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); |
| 200 | /* Make a delay. MPC5200 spec says 25 usec min */ |
| 201 | udelay(500000); |
| 202 | } else |
| 203 | setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4); |
| 204 | } |
| 205 | #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */ |