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git01.mediatek.com / filogic / uboot / 94c3502155bbcf5ace3eb9c5d21b861ec3180b9a / . / board / dvlhost / u-boot.lds
blob: 40c9c8038bb1e88110172680151a8223a8b2c790 [file] [log] [blame]
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]6 */
7
8OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
9OUTPUT_ARCH (arm)
10ENTRY (_start)
11SECTIONS
12{
13 . = 0x00000000;
14
15 . = ALIGN (4);
16 .text : {
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]17 *(.__image_copy_start)
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]18 arch/arm/cpu/ixp/start.o(.text*)
19 net/libnet.o(.text*)
20 board/dvlhost/libdvlhost.o(.text*)
21 arch/arm/cpu/ixp/libixp.o(.text*)
22 drivers/serial/libserial.o(.text*)
23
24 . = env_offset;
25 common/env_embedded.o(.ppcenv)
26 *(.text*)
27 }
28
29 . = ALIGN (4);
30 .rodata : {
31 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
32 }
33 . = ALIGN (4);
34 .data : {
35 *(.data*)
36 }
37 . = ALIGN (4);
38 .got : {
39 *(.got)
40 }
41 . =.;
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]42
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]43 . = ALIGN(4);
44 .u_boot_list : {
Albert ARIBAUDc24895e2013-02-25 00:59:00 +0000[diff] [blame]45 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut607092a2012-10-12 10:27:03 +0000[diff] [blame]46 }
47
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]48 . = ALIGN (4);
Benoît Thébaudeau03bae032013-04-11 09:35:46 +0000[diff] [blame]49
Albert ARIBAUDc53687e2013-06-11 14:17:33 +0200[diff] [blame]50 .image_copy_end :
51 {
52 *(.__image_copy_end)
53 }
Benoît Thébaudeau03bae032013-04-11 09:35:46 +0000[diff] [blame]54
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]55 .rel_dyn_start :
56 {
57 *(.__rel_dyn_start)
58 }
59
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]60 .rel.dyn : {
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]61 *(.rel*)
Albert ARIBAUDaf3ff162013-06-11 14:17:34 +0200[diff] [blame]62 }
63
64 .rel_dyn_end :
65 {
66 *(.__rel_dyn_end)
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]67 }
68
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]69 _end = .;
70
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]71/*
72 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
73 * __bss_base and __bss_limit are for linker only (overlay ordering)
74 */
75
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]76 .bss_start __rel_dyn_start (OVERLAY) : {
77 KEEP(*(.__bss_start));
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]78 __bss_base = .;
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]79 }
80
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]81 .bss __bss_base (OVERLAY) : {
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]82 *(.bss*)
83 . = ALIGN(4);
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]84 __bss_limit = .;
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]85 }
Albert ARIBAUDba5662d2013-04-11 05:43:21 +0000[diff] [blame]86 .bss_end __bss_limit (OVERLAY) : {
87 KEEP(*(.__bss_end));
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]88 }
Albert ARIBAUD436f6322013-02-25 00:58:59 +0000[diff] [blame]89
Albert ARIBAUD16915932013-06-11 14:17:31 +0200[diff] [blame]90 /DISCARD/ : { *(.dynsym) }
Michael Schwingend9fe6cc2011-05-23 00:00:09 +0200[diff] [blame]91 /DISCARD/ : { *(.dynstr*) }
92 /DISCARD/ : { *(.dynamic*) }
93 /DISCARD/ : { *(.plt*) }
94 /DISCARD/ : { *(.interp*) }
95 /DISCARD/ : { *(.gnu*) }
96}