Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 2 | /* |
| 3 | * ColdFire Internal Memory Map and Defines |
| 4 | * |
Alison Wang | fdc2fb1 | 2012-10-18 19:25:51 +0000 | [diff] [blame] | 5 | * Copyright 2004-2012 Freescale Semiconductor, Inc. |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __IMMAP_H |
| 10 | #define __IMMAP_H |
Stefan Roese | f111012 | 2007-07-16 13:11:12 +0200 | [diff] [blame] | 11 | |
TsiChung Liew | b354aef | 2009-06-12 11:29:00 +0000 | [diff] [blame] | 12 | #if defined(CONFIG_MCF520x) |
| 13 | #include <asm/immap_520x.h> |
| 14 | #include <asm/m520x.h> |
| 15 | |
| 16 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
| 17 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) |
| 18 | |
| 19 | /* Timer */ |
| 20 | #ifdef CONFIG_MCFTMR |
| 21 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 22 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 23 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 24 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) |
| 25 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) |
| 26 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 27 | #define CONFIG_SYS_TMRINTR_PRI (6) |
| 28 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 29 | #endif |
| 30 | |
| 31 | #ifdef CONFIG_MCFPIT |
| 32 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 33 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 34 | #define CONFIG_SYS_PIT_PRESCALE (6) |
| 35 | #endif |
| 36 | |
| 37 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 38 | #define CONFIG_SYS_NUM_IRQS (128) |
| 39 | #endif /* CONFIG_M520x */ |
| 40 | |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 41 | #ifdef CONFIG_M52277 |
| 42 | #include <asm/immap_5227x.h> |
| 43 | #include <asm/m5227x.h> |
| 44 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 46 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 48 | |
| 49 | #ifdef CONFIG_LCD |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 50 | #define CONFIG_SYS_LCD_BASE (MMAP_LCD) |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 51 | #endif |
| 52 | |
| 53 | /* Timer */ |
| 54 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 56 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 57 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 58 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) |
| 59 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) |
| 60 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 61 | #define CONFIG_SYS_TMRINTR_PRI (6) |
| 62 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 63 | #endif |
| 64 | |
| 65 | #ifdef CONFIG_MCFPIT |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 67 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 68 | #define CONFIG_SYS_PIT_PRESCALE (6) |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 69 | #endif |
| 70 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 72 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | 99b037a | 2008-01-14 17:43:33 -0600 | [diff] [blame] | 73 | #endif /* CONFIG_M52277 */ |
| 74 | |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 75 | #ifdef CONFIG_M5235 |
| 76 | #include <asm/immap_5235.h> |
| 77 | #include <asm/m5235.h> |
| 78 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) |
| 80 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 81 | |
| 82 | /* Timer */ |
| 83 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 85 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) |
| 86 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) |
| 87 | #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) |
| 88 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) |
| 89 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 90 | #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ |
| 91 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 92 | #endif |
| 93 | |
| 94 | #ifdef CONFIG_MCFPIT |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 96 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 97 | #define CONFIG_SYS_PIT_PRESCALE (6) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 98 | #endif |
| 99 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 101 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | b859ef1 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 102 | #endif /* CONFIG_M5235 */ |
| 103 | |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 104 | #ifdef CONFIG_M5249 |
| 105 | #include <asm/immap_5249.h> |
| 106 | #include <asm/m5249.h> |
| 107 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC) |
| 111 | #define CONFIG_SYS_NUM_IRQS (64) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 112 | |
| 113 | /* Timer */ |
| 114 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 116 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 117 | #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) |
| 118 | #define CONFIG_SYS_TMRINTR_NO (31) |
| 119 | #define CONFIG_SYS_TMRINTR_MASK (0x00000400) |
| 120 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 121 | #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) |
| 122 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 123 | #endif |
| 124 | #endif /* CONFIG_M5249 */ |
| 125 | |
TsiChungLiew | 3467469 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 126 | #ifdef CONFIG_M5253 |
| 127 | #include <asm/immap_5253.h> |
| 128 | #include <asm/m5249.h> |
| 129 | #include <asm/m5253.h> |
| 130 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
TsiChungLiew | 3467469 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 132 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC) |
| 134 | #define CONFIG_SYS_NUM_IRQS (64) |
TsiChungLiew | 3467469 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 135 | |
| 136 | /* Timer */ |
| 137 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 139 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 140 | #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) |
| 141 | #define CONFIG_SYS_TMRINTR_NO (27) |
| 142 | #define CONFIG_SYS_TMRINTR_MASK (0x00000400) |
| 143 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 144 | #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) |
| 145 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) |
TsiChungLiew | 3467469 | 2007-08-16 13:20:50 -0500 | [diff] [blame] | 146 | #endif |
| 147 | #endif /* CONFIG_M5253 */ |
| 148 | |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 149 | #ifdef CONFIG_M5271 |
| 150 | #include <asm/immap_5271.h> |
| 151 | #include <asm/m5271.h> |
| 152 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) |
| 154 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 155 | |
| 156 | /* Timer */ |
| 157 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 159 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) |
| 160 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) |
| 161 | #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) |
| 162 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) |
| 163 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
Richard Retanubun | 0dd9431 | 2009-03-26 15:26:01 -0400 | [diff] [blame] | 164 | #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 166 | #endif |
| 167 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 169 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 170 | #endif /* CONFIG_M5271 */ |
| 171 | |
| 172 | #ifdef CONFIG_M5272 |
| 173 | #include <asm/immap_5272.h> |
| 174 | #include <asm/m5272.h> |
| 175 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) |
| 177 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 178 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 179 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC) |
| 180 | #define CONFIG_SYS_NUM_IRQS (64) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 181 | |
| 182 | /* Timer */ |
| 183 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) |
| 185 | #define CONFIG_SYS_TMR_BASE (MMAP_TMR3) |
| 186 | #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) |
| 187 | #define CONFIG_SYS_TMRINTR_NO (INT_TMR3) |
| 188 | #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) |
| 189 | #define CONFIG_SYS_TMRINTR_PEND (0) |
| 190 | #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) |
| 191 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 192 | #endif |
| 193 | #endif /* CONFIG_M5272 */ |
| 194 | |
Matthew Fettke | 761e2e9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 195 | #ifdef CONFIG_M5275 |
| 196 | #include <asm/immap_5275.h> |
| 197 | #include <asm/m5275.h> |
| 198 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
| 200 | #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) |
| 201 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
Matthew Fettke | 761e2e9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 202 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 204 | #define CONFIG_SYS_NUM_IRQS (192) |
Matthew Fettke | 761e2e9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 205 | |
| 206 | /* Timer */ |
| 207 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 209 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) |
| 210 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) |
| 211 | #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) |
| 212 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) |
| 213 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 214 | #define CONFIG_SYS_TMRINTR_PRI (0x1E) |
| 215 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
Matthew Fettke | 761e2e9 | 2008-02-04 15:38:20 -0600 | [diff] [blame] | 216 | #endif |
| 217 | #endif /* CONFIG_M5275 */ |
| 218 | |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 219 | #ifdef CONFIG_M5282 |
| 220 | #include <asm/immap_5282.h> |
| 221 | #include <asm/m5282.h> |
| 222 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) |
| 224 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 225 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 227 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 228 | |
| 229 | /* Timer */ |
| 230 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 232 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) |
| 233 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) |
| 234 | #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) |
| 235 | #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) |
| 236 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 237 | #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ |
| 238 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | 0e81abc | 2007-08-15 19:38:15 -0500 | [diff] [blame] | 239 | #endif |
| 240 | #endif /* CONFIG_M5282 */ |
| 241 | |
angelo@sysam.it | bb4ba2c | 2015-02-12 01:40:00 +0100 | [diff] [blame] | 242 | #ifdef CONFIG_M5307 |
| 243 | #include <asm/immap_5307.h> |
| 244 | #include <asm/m5307.h> |
| 245 | |
| 246 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ |
| 247 | (CONFIG_SYS_UART_PORT * 0x40)) |
| 248 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC) |
| 249 | #define CONFIG_SYS_NUM_IRQS (64) |
| 250 | |
| 251 | /* Timer */ |
| 252 | #ifdef CONFIG_MCFTMR |
| 253 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 254 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 255 | #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ |
| 256 | (CONFIG_SYS_INTR_BASE))->ipr) |
| 257 | #define CONFIG_SYS_TMRINTR_NO (31) |
| 258 | #define CONFIG_SYS_TMRINTR_MASK (0x00000400) |
| 259 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 260 | #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ |
| 261 | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) |
| 262 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 263 | #endif |
| 264 | #endif /* CONFIG_M5307 */ |
| 265 | |
TsiChung Liew | e7e4fc8 | 2008-10-22 11:38:21 +0000 | [diff] [blame] | 266 | #if defined(CONFIG_MCF5301x) |
| 267 | #include <asm/immap_5301x.h> |
| 268 | #include <asm/m5301x.h> |
| 269 | |
| 270 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
| 271 | #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) |
| 272 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) |
| 273 | |
| 274 | #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) |
| 275 | |
| 276 | /* Timer */ |
| 277 | #ifdef CONFIG_MCFTMR |
| 278 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 279 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 280 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 281 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) |
| 282 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) |
| 283 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 284 | #define CONFIG_SYS_TMRINTR_PRI (6) |
| 285 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 286 | #endif |
| 287 | |
| 288 | #ifdef CONFIG_MCFPIT |
| 289 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 290 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 291 | #define CONFIG_SYS_PIT_PRESCALE (6) |
| 292 | #endif |
| 293 | |
| 294 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 295 | #define CONFIG_SYS_NUM_IRQS (128) |
| 296 | #endif /* CONFIG_M5301x */ |
| 297 | |
TsiChungLiew | 6f8a0a3 | 2008-01-14 17:23:08 -0600 | [diff] [blame] | 298 | #if defined(CONFIG_M5329) || defined(CONFIG_M5373) |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 299 | #include <asm/immap_5329.h> |
| 300 | #include <asm/m5329.h> |
| 301 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) |
| 303 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) |
| 304 | #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 305 | |
| 306 | /* Timer */ |
| 307 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 309 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 310 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 311 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) |
| 312 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) |
| 313 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 314 | #define CONFIG_SYS_TMRINTR_PRI (6) |
| 315 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 316 | #endif |
| 317 | |
| 318 | #ifdef CONFIG_MCFPIT |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 319 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 320 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 321 | #define CONFIG_SYS_PIT_PRESCALE (6) |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 322 | #endif |
| 323 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 324 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 325 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | 6f8a0a3 | 2008-01-14 17:23:08 -0600 | [diff] [blame] | 326 | #endif /* CONFIG_M5329 && CONFIG_M5373 */ |
Stefan Roese | f111012 | 2007-07-16 13:11:12 +0200 | [diff] [blame] | 327 | |
Alison Wang | fdc2fb1 | 2012-10-18 19:25:51 +0000 | [diff] [blame] | 328 | #if defined(CONFIG_M54418) |
| 329 | #include <asm/immap_5441x.h> |
| 330 | #include <asm/m5441x.h> |
| 331 | |
| 332 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
| 333 | #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) |
| 334 | |
| 335 | #if (CONFIG_SYS_UART_PORT < 4) |
| 336 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ |
| 337 | (CONFIG_SYS_UART_PORT * 0x4000)) |
| 338 | #else |
| 339 | #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ |
| 340 | ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) |
| 341 | #endif |
| 342 | |
| 343 | #define MMAP_DSPI MMAP_DSPI0 |
| 344 | #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) |
| 345 | |
| 346 | /* Timer */ |
| 347 | #ifdef CONFIG_MCFTMR |
| 348 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 349 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 350 | #define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 351 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) |
| 352 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) |
| 353 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 354 | #define CONFIG_SYS_TMRINTR_PRI (6) |
| 355 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
| 356 | #endif |
| 357 | |
| 358 | #ifdef CONFIG_MCFPIT |
| 359 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 360 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 361 | #define CONFIG_SYS_PIT_PRESCALE (6) |
| 362 | #endif |
| 363 | |
| 364 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
Angelo Dureghello | e2f9393 | 2018-02-04 21:13:12 +0100 | [diff] [blame] | 365 | #define CONFIG_SYS_NUM_IRQS (192) |
Alison Wang | fdc2fb1 | 2012-10-18 19:25:51 +0000 | [diff] [blame] | 366 | |
| 367 | #endif /* CONFIG_M54418 */ |
| 368 | |
TsiChung Liew | 3cdc00a | 2008-08-11 13:41:49 +0000 | [diff] [blame] | 369 | #if defined(CONFIG_M54451) || defined(CONFIG_M54455) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 370 | #include <asm/immap_5445x.h> |
| 371 | #include <asm/m5445x.h> |
| 372 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 373 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
TsiChung Liew | 3cdc00a | 2008-08-11 13:41:49 +0000 | [diff] [blame] | 374 | #if defined(CONFIG_M54455EVB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 375 | #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) |
TsiChung Liew | 3cdc00a | 2008-08-11 13:41:49 +0000 | [diff] [blame] | 376 | #endif |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 377 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 379 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 380 | #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 381 | |
| 382 | /* Timer */ |
| 383 | #ifdef CONFIG_MCFTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 384 | #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) |
| 385 | #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) |
| 386 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 387 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) |
| 388 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) |
| 389 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 390 | #define CONFIG_SYS_TMRINTR_PRI (6) |
| 391 | #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 392 | #endif |
| 393 | |
| 394 | #ifdef CONFIG_MCFPIT |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 395 | #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0) |
| 396 | #define CONFIG_SYS_PIT_BASE (MMAP_PIT1) |
| 397 | #define CONFIG_SYS_PIT_PRESCALE (6) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 398 | #endif |
| 399 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 400 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 401 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 402 | |
| 403 | #ifdef CONFIG_PCI |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 404 | #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) |
| 405 | #define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) |
| 406 | #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) |
| 407 | #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 408 | #endif |
TsiChung Liew | 3cdc00a | 2008-08-11 13:41:49 +0000 | [diff] [blame] | 409 | #endif /* CONFIG_M54451 || CONFIG_M54455 */ |
TsiChungLiew | fc3ca3b | 2007-08-16 15:05:11 -0500 | [diff] [blame] | 410 | |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 411 | #ifdef CONFIG_M547x |
| 412 | #include <asm/immap_547x_8x.h> |
| 413 | #include <asm/m547x_8x.h> |
| 414 | |
| 415 | #ifdef CONFIG_FSLDMAFEC |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 416 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
| 417 | #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 418 | |
| 419 | #define FEC0_RX_TASK 0 |
| 420 | #define FEC0_TX_TASK 1 |
| 421 | #define FEC0_RX_PRIORITY 6 |
| 422 | #define FEC0_TX_PRIORITY 7 |
| 423 | #define FEC0_RX_INIT 16 |
| 424 | #define FEC0_TX_INIT 17 |
| 425 | #define FEC1_RX_TASK 2 |
| 426 | #define FEC1_TX_TASK 3 |
| 427 | #define FEC1_RX_PRIORITY 6 |
| 428 | #define FEC1_TX_PRIORITY 7 |
| 429 | #define FEC1_RX_INIT 30 |
| 430 | #define FEC1_TX_INIT 31 |
| 431 | #endif |
| 432 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 433 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 434 | |
| 435 | #ifdef CONFIG_SLTTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 436 | #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) |
| 437 | #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) |
| 438 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 439 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) |
| 440 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) |
| 441 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 442 | #define CONFIG_SYS_TMRINTR_PRI (0x1E) |
| 443 | #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 444 | #endif |
| 445 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 446 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 447 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 448 | |
| 449 | #ifdef CONFIG_PCI |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 450 | #define CONFIG_SYS_PCI_BAR0 (0x40000000) |
| 451 | #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) |
| 452 | #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) |
| 453 | #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 454 | #endif |
| 455 | #endif /* CONFIG_M547x */ |
| 456 | |
| 457 | #ifdef CONFIG_M548x |
| 458 | #include <asm/immap_547x_8x.h> |
| 459 | #include <asm/m547x_8x.h> |
| 460 | |
| 461 | #ifdef CONFIG_FSLDMAFEC |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 462 | #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) |
| 463 | #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 464 | |
| 465 | #define FEC0_RX_TASK 0 |
| 466 | #define FEC0_TX_TASK 1 |
| 467 | #define FEC0_RX_PRIORITY 6 |
| 468 | #define FEC0_TX_PRIORITY 7 |
| 469 | #define FEC0_RX_INIT 16 |
| 470 | #define FEC0_TX_INIT 17 |
| 471 | #define FEC1_RX_TASK 2 |
| 472 | #define FEC1_TX_TASK 3 |
| 473 | #define FEC1_RX_PRIORITY 6 |
| 474 | #define FEC1_TX_PRIORITY 7 |
| 475 | #define FEC1_RX_INIT 30 |
| 476 | #define FEC1_TX_INIT 31 |
| 477 | #endif |
| 478 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 479 | #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 480 | |
| 481 | /* Timer */ |
| 482 | #ifdef CONFIG_SLTTMR |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 483 | #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) |
| 484 | #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) |
| 485 | #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) |
| 486 | #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) |
| 487 | #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) |
| 488 | #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) |
| 489 | #define CONFIG_SYS_TMRINTR_PRI (0x1E) |
| 490 | #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 491 | #endif |
| 492 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 493 | #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) |
| 494 | #define CONFIG_SYS_NUM_IRQS (128) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 495 | |
| 496 | #ifdef CONFIG_PCI |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 497 | #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) |
| 498 | #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) |
| 499 | #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) |
| 500 | #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) |
TsiChungLiew | 471b2c6 | 2008-01-15 13:39:44 -0600 | [diff] [blame] | 501 | #endif |
| 502 | #endif /* CONFIG_M548x */ |
| 503 | |
TsiChungLiew | 2e0aeef | 2007-07-05 22:39:07 -0500 | [diff] [blame] | 504 | #endif /* __IMMAP_H */ |