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git01.mediatek.com / filogic / uboot / 947fdb6653063540d6d4a31c30e7bd6a31c76461 / . / arch / arm / dts / zynqmp-vpk120-revA.dts
blob: 4768fac71d023bcead454f2ff3976e86b2238620 [file] [log] [blame]
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx ZynqMP VPK120 RevA System Controller
4 *
5 * (C) Copyright 2021 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20 model = "ZynqMP System Controller on VPK120 board RevA";
21 compatible = "xlnx,zynqmp-vpk120-revA",
22 "xlnx,zynqmp-vpk120", "xlnx,zynqmp";
23
24 aliases {
25 ethernet0 = &gem0;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 mmc0 = &sdhci0;
29 serial0 = &uart0;
30 serial1 = &dcc;
31 spi0 = &qspi;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 nvmem0 = &eeprom;
35 };
36
37 chosen {
38 bootargs = "earlycon";
39 stdout-path = "serial0:115200n8";
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>;
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49 autorepeat;
Michal Simek518d1662024-03-08 09:40:52 +0100[diff] [blame]50 button-16 {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]51 label = "sw16";
52 gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
53 linux,code = <BTN_MISC>;
54 wakeup-source;
55 autorepeat;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 heartbeat-led { /* ds40 */
62 label = "heartbeat";
63 gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]68 si5332_0: si5332-0 { /* ps_ref_clk */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <33333333>;
72 };
73
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]74 si5332_1: si5332-1 { /* clk0_sgmii */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <33333333>; /* FIXME */
78 };
79
Michal Simeke3157622024-01-08 10:24:45 +0100[diff] [blame]80 si5332_2: si5332-2 { /* clk1_usb */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <27000000>;
84 };
85};
86
87&qspi { /* MIO 0-5 */
88 status = "okay";
89 flash@0 {
90 compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */
91 #address-cells = <1>;
92 #size-cells = <1>;
93 reg = <0>;
94 spi-tx-bus-width = <4>;
95 spi-rx-bus-width = <4>;
96 spi-max-frequency = <108000000>;
97 partition@0 { /* for testing purpose */
98 label = "qspi";
99 reg = <0 0x4000000>;
100 };
101 };
102};
103
104&sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */
105 status = "okay";
106 non-removable;
107 disable-wp;
108 bus-width = <8>;
109 xlnx,mio-bank = <0>;
110};
111
112&uart0 { /* uart0 MIO38-39 */
113 status = "okay";
114 bootph-all;
115};
116
117&gem0 {
118 status = "okay";
119 phy-handle = <&phy0>;
120 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]121 /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */
Michal Simek3181a872023-10-12 14:58:47 +0200[diff] [blame]122 mdio: mdio {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
126 phy0: ethernet-phy@0 {
127 reg = <0>;
128 };
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]129 };
130};
131
132&gpio {
133 status = "okay";
134 gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
135 "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */
136 "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
137 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
138 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
139 "", "", "", "", "", /* 25 - 29 */
140 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
141 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
142 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
143 "", "", "", "", "", /* 45 - 49 */
144 "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
145 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
146 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
147 "", "", "", "", "", /* 65 - 69 */
148 "", "", "", "", "", /* 70 - 74 */
149 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
150 "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
151 "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
152 "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
153 "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
154 "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
155 "", "", "", "", "", /* 100 - 104 */
156 "", "", "", "", "", /* 105 - 109 */
157 "", "", "", "", "", /* 110 - 114 */
158 "", "", "", "", "", /* 115 - 119 */
159 "", "", "", "", "", /* 120 - 124 */
160 "", "", "", "", "", /* 125 - 129 */
161 "", "", "", "", "", /* 130 - 134 */
162 "", "", "", "", "", /* 135 - 139 */
163 "", "", "", "", "", /* 140 - 144 */
164 "", "", "", "", "", /* 145 - 149 */
165 "", "", "", "", "", /* 150 - 154 */
166 "", "", "", "", "", /* 155 - 159 */
167 "", "", "", "", "", /* 160 - 164 */
168 "", "", "", "", "", /* 165 - 169 */
169 "", "", "", ""; /* 170 - 173 */
170};
171
172&i2c0 { /* MIO 34-35 - can't stay here */
173 status = "okay";
174 clock-frequency = <400000>;
175 pinctrl-names = "default", "gpio";
176 pinctrl-0 = <&pinctrl_i2c0_default>;
177 pinctrl-1 = <&pinctrl_i2c0_gpio>;
178 scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
179 sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
180
181 tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */
182 compatible = "ti,tca6416";
183 reg = <0x20>;
184 gpio-controller; /* interrupt not connected */
185 #gpio-cells = <2>;
186 gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */
187 "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */
188 "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */
189 "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */
190 };
191
192 i2c-mux@74 { /* u33 */
193 compatible = "nxp,pca9548";
194 #address-cells = <1>;
195 #size-cells = <0>;
196 reg = <0x74>;
197 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
198 pmbus_i2c: i2c@0 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <0>;
202 /* On connector J325 */
203 ir38060_41: regulator@41 { /* IR38060 - u259 */
204 compatible = "infineon,ir38060", "infineon,ir38064";
205 reg = <0x41>; /* i2c addr 0x11 */
206 };
207 ir38164_43: regulator@43 { /* IR38164 - u13 */
208 compatible = "infineon,ir38164";
209 reg = <0x43>; /* i2c addr 0x13 */
210 };
211 ir35221_45: pmic@46 { /* IR35221 - u152 */
212 compatible = "infineon,ir35221";
213 reg = <0x46>; /* PMBUS - 0x16 */
214 };
215 irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */
216 compatible = "infineon,irps5401";
217 reg = <0x47>; /* i2c addr 0x17 */
218 };
219 ir38164_49: regulator@49 { /* IR38164 - u189 */
220 compatible = "infineon,ir38164";
221 reg = <0x49>; /* i2c addr 0x19 */
222 };
223 irps5401_4c: pmic@4c { /* IRPS5401 - u167 */
224 compatible = "infineon,irps5401";
225 reg = <0x4c>; /* i2c addr 0x1c */
226 };
227 irps5401_4d: pmic@4d { /* IRPS5401 - u175 */
228 compatible = "infineon,irps5401";
229 reg = <0x4d>; /* i2c addr 0x1c */
230 };
231 ir38164_4e: regulator@4e { /* IR38164 - u184 */
232 compatible = "infineon,ir38164";
233 reg = <0x4e>; /* i2c addr 0x1e */
234 };
235 ir38164_4f: regulator@4f { /* IR38164 - u187 */
236 compatible = "infineon,ir38164";
237 reg = <0x4f>; /* i2c addr 0x1f */
238 };
239 };
240 pmbus1_ina226_i2c: i2c@1 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <1>;
244 /* FIXME check alerts coming to SC */
245 vccint: ina226@40 { /* u65 */
246 compatible = "ti,ina226";
247 reg = <0x40>;
248 shunt-resistor = <5000>;
249 };
250 vcc_soc: ina226@41 { /* u161 */
251 compatible = "ti,ina226";
252 reg = <0x41>;
253 shunt-resistor = <5000>;
254 };
255 vcc_pmc: ina226@42 { /* u163 */
256 compatible = "ti,ina226";
257 reg = <0x42>;
258 shunt-resistor = <5000>;
259 };
260 vcc_ram: ina226@43 { /* u5 */
261 compatible = "ti,ina226";
262 reg = <0x43>;
263 shunt-resistor = <5000>;
264 };
265 vcc_pslp: ina226@44 { /* u165 */
266 compatible = "ti,ina226";
267 reg = <0x44>;
268 shunt-resistor = <5000>;
269 };
270 vcc_psfp: ina226@45 { /* u164 */
271 compatible = "ti,ina226";
272 reg = <0x45>;
273 shunt-resistor = <5000>;
274 };
275 };
276 i2c@2 { /* NC */ /* FIXME maybe remove */
277 #address-cells = <1>;
278 #size-cells = <0>;
279 reg = <2>;
280 };
281 pmbus2_ina226_i2c: i2c@3 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 reg = <3>;
285 /* FIXME check alerts coming to SC */
286 vccaux: ina226@40 { /* u166 */
287 compatible = "ti,ina226";
288 reg = <0x40>;
289 shunt-resistor = <5000>;
290 };
291 vccaux_pmc: ina226@41 { /* u168 */
292 compatible = "ti,ina226";
293 reg = <0x41>;
294 shunt-resistor = <5000>;
295 };
296 mgtavcc: ina226@42 { /* u265 */
297 compatible = "ti,ina226";
298 reg = <0x42>;
299 shunt-resistor = <5000>;
300 };
301 vcc1v5: ina226@43 { /* u264 */
302 compatible = "ti,ina226";
303 reg = <0x43>;
304 shunt-resistor = <5000>;
305 };
306 vcco_mio: ina226@45 { /* u172 */
307 compatible = "ti,ina226";
308 reg = <0x45>;
309 shunt-resistor = <5000>;
310 };
311 mgtavtt: ina226@46 { /* u188 */
312 compatible = "ti,ina226";
313 reg = <0x46>;
314 shunt-resistor = <2000>;
315 };
316 vcco_502: ina226@47 { /* u174 */
317 compatible = "ti,ina226";
318 reg = <0x47>;
319 shunt-resistor = <5000>;
320 };
321 mgtvccaux: ina226@48 { /* u176 */
322 compatible = "ti,ina226";
323 reg = <0x48>;
324 shunt-resistor = <5000>;
325 };
326 vcc1v1_lp4: ina226@49 { /* u186 */
327 compatible = "ti,ina226";
328 reg = <0x49>;
329 shunt-resistor = <2000>;
330 };
331 vadj_fmc: ina226@4a { /* u184 */
332 compatible = "ti,ina226";
333 reg = <0x4a>;
334 shunt-resistor = <2000>;
335 };
336 lpdmgtyavcc: ina226@4b { /* u177 */
337 compatible = "ti,ina226";
338 reg = <0x4b>;
339 shunt-resistor = <5000>;
340 };
341 lpdmgtyavtt: ina226@4c { /* u260 */
342 compatible = "ti,ina226";
343 reg = <0x4c>;
344 shunt-resistor = <2000>;
345 };
346 lpdmgtyvccaux: ina226@4d { /* u234 */
347 compatible = "ti,ina226";
348 reg = <0x4d>;
349 shunt-resistor = <5000>;
350 };
351 };
352 i2c@4 { /* NC */
353 #address-cells = <1>;
354 #size-cells = <0>;
355 reg = <4>;
356 };
357 i2c@5 { /* NC */
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <5>;
361 };
362 user_si570: i2c@6 {
363 #address-cells = <1>;
364 #size-cells = <0>;
365 reg = <6>;
366 user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */
367 #clock-cells = <0>;
368 compatible = "silabs,si570";
369 reg = <0x5f>;
370 temperature-stability = <50>;
371 factory-fout = <100000000>;
372 clock-frequency = <100000000>;
373 clock-output-names = "fmc_si570";
374 };
375
376 };
377 /* 7 unused */
378 };
379};
380
381&i2c1 { /* i2c1 MIO 36-37 */
382 status = "okay";
383 clock-frequency = <400000>;
384 pinctrl-names = "default", "gpio";
385 pinctrl-0 = <&pinctrl_i2c1_default>;
386 pinctrl-1 = <&pinctrl_i2c1_gpio>;
387 scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
388 sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
389
390 i2c-mux@74 { /* u35 */
391 compatible = "nxp,pca9548";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <0x74>;
395 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
396 ref_clk_i2c: i2c@0 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 reg = <0>;
400 /* Use for storing information about SC board */
401 eeprom: eeprom@54 { /* u34 - m24128 16kB */
402 compatible = "st,24c128", "atmel,24c128";
403 reg = <0x54>; /* & 0x5c */
404 };
405 ref_clk: clock-generator@5d { /* u32 */
406 #clock-cells = <0>;
407 compatible = "silabs,si570";
408 reg = <0x5d>;
409 temperature-stability = <50>;
410 factory-fout = <33333333>;
411 clock-frequency = <33333333>;
412 clock-output-names = "ref_clk";
413 silabs,skip-recall;
414 };
415 };
416 fmcp1_i2c: i2c@1 {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 reg = <1>;
420 /* FIXME connection to Samtec J51C */
421 /* expected eeprom 0x50 SE cards */
422 };
423 i2c@2 { /* NC - FIXME */
424 #address-cells = <1>;
425 #size-cells = <0>;
426 reg = <2>;
427 };
428 lpddr4_si570_clk3_i2c: i2c@3 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 reg = <3>;
432 lpddr4_clk3: clock-generator@60 { /* u4 */
433 #clock-cells = <0>;
434 compatible = "silabs,si570";
435 reg = <0x60>;
436 temperature-stability = <50>;
437 factory-fout = <200000000>;
438 clock-frequency = <200000000>;
439 clock-output-names = "lpddr4_clk3";
440 };
441 };
442 lpddr4_si570_clk2_i2c: i2c@4 {
443 #address-cells = <1>;
444 #size-cells = <0>;
445 reg = <4>;
446 lpddr4_clk2: clock-generator@60 { /* u3 */
447 #clock-cells = <0>;
448 compatible = "silabs,si570";
449 reg = <0x60>;
450 temperature-stability = <50>;
451 factory-fout = <200000000>;
452 clock-frequency = <200000000>;
453 clock-output-names = "lpddr4_clk2";
454 };
455 };
456 lpddr4_si570_clk1_i2c: i2c@5 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 reg = <5>;
460 lpddr4_clk1: clock-generator@60 { /* u248 */
461 #clock-cells = <0>;
462 compatible = "silabs,si570";
463 reg = <0x60>;
464 temperature-stability = <50>;
465 factory-fout = <200000000>;
466 clock-frequency = <200000000>;
467 clock-output-names = "lpddr4_clk1";
468 };
469 };
470 qsfpdd_i2c: i2c@6 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <6>;
474 /* J1/J2 connectors */
475 };
476 idt8a34001_i2c: i2c@7 {
477 #address-cells = <1>;
478 #size-cells = <0>;
479 reg = <7>;
480 /* Via J310 connector */
481 idt_8a34001: phc@5b {
482 compatible = "idt,8a34001"; /* u219B */
483 reg = <0x5b>; /* FIXME not in schematics */
484 };
485 };
486 };
487};
488
489&usb0 { /* MIO52 - MIO63 */
490 status = "okay";
491 phy-names = "usb3-phy";
492 phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
493};
494
495&psgtr {
496 status = "okay";
497 /* sgmii, usb3 */
498 clocks = <&si5332_1>, <&si5332_2>;
499 clock-names = "ref0", "ref1";
500};
501
502&dwc3_0 {
503 status = "okay";
504 dr_mode = "peripheral";
505 snps,dis_u2_susphy_quirk;
506 snps,dis_u3_susphy_quirk;
507 maximum-speed = "super-speed";
508};
509
510&xilinx_ams {
511 status = "okay";
512};
513
514&ams_ps {
515 status = "okay";
516};
517
518&ams_pl {
519 status = "okay";
520};
521
522&pinctrl0 {
523 status = "okay";
524 pinctrl_i2c0_default: i2c0-default {
525 mux {
526 groups = "i2c0_8_grp";
527 function = "i2c0";
528 };
529
530 conf {
531 groups = "i2c0_8_grp";
532 bias-pull-up;
533 slew-rate = <SLEW_RATE_SLOW>;
534 power-source = <IO_STANDARD_LVCMOS18>;
535 };
536 };
537
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame]538 pinctrl_i2c0_gpio: i2c0-gpio-grp {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]539 mux {
540 groups = "gpio0_34_grp", "gpio0_35_grp";
541 function = "gpio0";
542 };
543
544 conf {
545 groups = "gpio0_34_grp", "gpio0_35_grp";
546 slew-rate = <SLEW_RATE_SLOW>;
547 power-source = <IO_STANDARD_LVCMOS18>;
548 };
549 };
550
551 pinctrl_i2c1_default: i2c1-default {
552 mux {
553 groups = "i2c1_9_grp";
554 function = "i2c1";
555 };
556
557 conf {
558 groups = "i2c1_9_grp";
559 bias-pull-up;
560 slew-rate = <SLEW_RATE_SLOW>;
561 power-source = <IO_STANDARD_LVCMOS18>;
562 };
563 };
564
Michal Simekcf3cd802023-12-19 17:16:50 +0100[diff] [blame]565 pinctrl_i2c1_gpio: i2c1-gpio-grp {
Michal Simek62a01fe2023-09-27 11:53:31 +0200[diff] [blame]566 mux {
567 groups = "gpio0_36_grp", "gpio0_37_grp";
568 function = "gpio0";
569 };
570
571 conf {
572 groups = "gpio0_36_grp", "gpio0_37_grp";
573 slew-rate = <SLEW_RATE_SLOW>;
574 power-source = <IO_STANDARD_LVCMOS18>;
575 };
576 };
577};