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git01.mediatek.com / filogic / uboot / 94483d21da93ff29a786ee00944e30466d0a2ab6 / . / post / lib_powerpc / cpu.c
blob: 98a8c6392c3a22fa6ecc97353100b699a87e48a2 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]2/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]5 */
6
7#include <common.h>
Simon Glass1d91ba72019-11-14 12:57:37 -0700[diff] [blame]8#include <cpu_func.h>
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]9
10/*
11 * CPU test
12 *
13 * This test checks the arithmetic logic unit (ALU) of CPU.
14 * It tests independently various groups of instructions using
15 * run-time modification of the code to reduce the memory footprint.
16 * For more details refer to post/cpu/ *.c files.
17 */
18
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]19#include <watchdog.h>
20#include <post.h>
Stefan Roesebc5591f2007-10-31 20:51:10 +0100[diff] [blame]21#include <asm/mmu.h>
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]22
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500[diff] [blame]23#if CFG_POST & CFG_SYS_POST_CPU
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]24
25extern int cpu_post_test_cmp (void);
26extern int cpu_post_test_cmpi (void);
27extern int cpu_post_test_two (void);
28extern int cpu_post_test_twox (void);
29extern int cpu_post_test_three (void);
30extern int cpu_post_test_threex (void);
31extern int cpu_post_test_threei (void);
32extern int cpu_post_test_andi (void);
33extern int cpu_post_test_srawi (void);
34extern int cpu_post_test_rlwnm (void);
35extern int cpu_post_test_rlwinm (void);
36extern int cpu_post_test_rlwimi (void);
37extern int cpu_post_test_store (void);
38extern int cpu_post_test_load (void);
39extern int cpu_post_test_cr (void);
40extern int cpu_post_test_b (void);
41extern int cpu_post_test_multi (void);
42extern int cpu_post_test_string (void);
43extern int cpu_post_test_complex (void);
44
45ulong cpu_post_makecr (long v)
46{
47 ulong cr = 0;
48
49 if (v < 0)
50 cr |= 0x80000000;
51 if (v > 0)
52 cr |= 0x40000000;
53 if (v == 0)
54 cr |= 0x20000000;
55
56 return cr;
57}
58
59int cpu_post_test (int flags)
60{
Simon Glassfbf091b2019-11-14 12:57:36 -0700[diff] [blame]61 int ic = icache_status();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]62 int ret = 0;
63
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]64 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]65 if (ic)
Simon Glassfbf091b2019-11-14 12:57:36 -0700[diff] [blame]66 icache_disable();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]67
68 if (ret == 0)
69 ret = cpu_post_test_cmp ();
70 if (ret == 0)
71 ret = cpu_post_test_cmpi ();
72 if (ret == 0)
73 ret = cpu_post_test_two ();
74 if (ret == 0)
75 ret = cpu_post_test_twox ();
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]76 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]77 if (ret == 0)
78 ret = cpu_post_test_three ();
79 if (ret == 0)
80 ret = cpu_post_test_threex ();
81 if (ret == 0)
82 ret = cpu_post_test_threei ();
83 if (ret == 0)
84 ret = cpu_post_test_andi ();
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]85 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]86 if (ret == 0)
87 ret = cpu_post_test_srawi ();
88 if (ret == 0)
89 ret = cpu_post_test_rlwnm ();
90 if (ret == 0)
91 ret = cpu_post_test_rlwinm ();
92 if (ret == 0)
93 ret = cpu_post_test_rlwimi ();
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]94 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]95 if (ret == 0)
96 ret = cpu_post_test_store ();
97 if (ret == 0)
98 ret = cpu_post_test_load ();
99 if (ret == 0)
100 ret = cpu_post_test_cr ();
101 if (ret == 0)
102 ret = cpu_post_test_b ();
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]103 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]104 if (ret == 0)
105 ret = cpu_post_test_multi ();
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]106 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]107 if (ret == 0)
108 ret = cpu_post_test_string ();
109 if (ret == 0)
110 ret = cpu_post_test_complex ();
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]111 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]112
113 if (ic)
Simon Glassfbf091b2019-11-14 12:57:36 -0700[diff] [blame]114 icache_enable();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]115
Stefan Roese80877fa2022-09-02 14:10:46 +0200[diff] [blame]116 schedule();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +0100[diff] [blame]117
118 return ret;
119}
120
Tom Rini3dd5d4a2022-12-04 10:14:17 -0500[diff] [blame]121#endif /* CFG_POST & CFG_SYS_POST_CPU */