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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass61612ed2014-11-24 21:18:18 -07002/*
3 * From Coreboot northbridge/intel/sandybridge/northbridge.c
4 *
5 * Copyright (C) 2007-2009 coresystems GmbH
6 * Copyright (C) 2011 The Chromium Authors
Simon Glass61612ed2014-11-24 21:18:18 -07007 */
8
9#include <common.h>
Simon Glass6b7f76d2016-01-17 16:11:27 -070010#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glass61612ed2014-11-24 21:18:18 -070012#include <asm/msr.h>
Simon Glass61612ed2014-11-24 21:18:18 -070013#include <asm/cpu.h>
Simon Glass55357302016-03-11 22:06:55 -070014#include <asm/intel_regs.h>
Simon Glass61612ed2014-11-24 21:18:18 -070015#include <asm/io.h>
16#include <asm/pci.h>
17#include <asm/processor.h>
18#include <asm/arch/pch.h>
19#include <asm/arch/model_206ax.h>
20#include <asm/arch/sandybridge.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
Simon Glass61612ed2014-11-24 21:18:18 -070022
Simon Glassd87b0922017-01-16 07:03:37 -070023DECLARE_GLOBAL_DATA_PTR;
24
Simon Glass11f76a72016-01-17 16:11:54 -070025int bridge_silicon_revision(struct udevice *dev)
Simon Glass61612ed2014-11-24 21:18:18 -070026{
Simon Glass11f76a72016-01-17 16:11:54 -070027 struct cpuid_result result;
28 u16 bridge_id;
29 u8 stepping;
Simon Glass61612ed2014-11-24 21:18:18 -070030
Simon Glass11f76a72016-01-17 16:11:54 -070031 result = cpuid(1);
32 stepping = result.eax & 0xf;
33 dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
34 bridge_id &= 0xf0;
35 return bridge_id | stepping;
Simon Glass61612ed2014-11-24 21:18:18 -070036}
37
Simon Glasse5bdccd2016-01-17 16:11:32 -070038static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len)
Simon Glass61612ed2014-11-24 21:18:18 -070039{
Simon Glass61612ed2014-11-24 21:18:18 -070040 u32 pciexbar_reg;
41
42 *base = 0;
43 *len = 0;
44
Simon Glasse5bdccd2016-01-17 16:11:32 -070045 dm_pci_read_config32(dev, PCIEXBAR, &pciexbar_reg);
Simon Glass61612ed2014-11-24 21:18:18 -070046
47 if (!(pciexbar_reg & (1 << 0)))
48 return 0;
49
50 switch ((pciexbar_reg >> 1) & 3) {
51 case 0: /* 256MB */
52 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
53 (1 << 28));
54 *len = 256 * 1024 * 1024;
55 return 1;
56 case 1: /* 128M */
57 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
58 (1 << 28) | (1 << 27));
59 *len = 128 * 1024 * 1024;
60 return 1;
61 case 2: /* 64M */
62 *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
63 (1 << 28) | (1 << 27) | (1 << 26));
64 *len = 64 * 1024 * 1024;
65 return 1;
66 }
67
68 return 0;
69}
70
Simon Glasse5bdccd2016-01-17 16:11:32 -070071static void add_fixed_resources(struct udevice *dev, int index)
Simon Glass61612ed2014-11-24 21:18:18 -070072{
73 u32 pcie_config_base, pcie_config_size;
74
Simon Glasse5bdccd2016-01-17 16:11:32 -070075 if (get_pcie_bar(dev, &pcie_config_base, &pcie_config_size)) {
Simon Glass61612ed2014-11-24 21:18:18 -070076 debug("Adding PCIe config bar base=0x%08x size=0x%x\n",
77 pcie_config_base, pcie_config_size);
78 }
79}
80
Simon Glass11f76a72016-01-17 16:11:54 -070081static void northbridge_dmi_init(struct udevice *dev, int rev)
Simon Glass61612ed2014-11-24 21:18:18 -070082{
83 /* Clear error status bits */
84 writel(0xffffffff, DMIBAR_REG(0x1c4));
85 writel(0xffffffff, DMIBAR_REG(0x1d0));
86
87 /* Steps prior to DMI ASPM */
Simon Glass11f76a72016-01-17 16:11:54 -070088 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
Simon Glass61612ed2014-11-24 21:18:18 -070089 clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
90 1 << 21);
91 }
92
93 setbits_le32(DMIBAR_REG(0x238), 1 << 29);
94
Simon Glass11f76a72016-01-17 16:11:54 -070095 if (rev >= SNB_STEP_D0) {
Simon Glass61612ed2014-11-24 21:18:18 -070096 setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
Simon Glass11f76a72016-01-17 16:11:54 -070097 } else if (rev >= SNB_STEP_D1) {
Simon Glass61612ed2014-11-24 21:18:18 -070098 clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
99 setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
100 }
101
102 /* Enable ASPM on SNB link, should happen before PCH link */
Simon Glass11f76a72016-01-17 16:11:54 -0700103 if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
Simon Glass61612ed2014-11-24 21:18:18 -0700104 setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
105
106 setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
107}
108
Simon Glass11f76a72016-01-17 16:11:54 -0700109static void northbridge_init(struct udevice *dev, int rev)
Simon Glass61612ed2014-11-24 21:18:18 -0700110{
111 u32 bridge_type;
112
113 add_fixed_resources(dev, 6);
Simon Glass11f76a72016-01-17 16:11:54 -0700114 northbridge_dmi_init(dev, rev);
Simon Glass61612ed2014-11-24 21:18:18 -0700115
116 bridge_type = readl(MCHBAR_REG(0x5f10));
117 bridge_type &= ~0xff;
118
Simon Glass11f76a72016-01-17 16:11:54 -0700119 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
Simon Glass61612ed2014-11-24 21:18:18 -0700120 /* Enable Power Aware Interrupt Routing - fixed priority */
121 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
122
123 /* 30h for IvyBridge */
124 bridge_type |= 0x30;
125 } else {
126 /* 20h for Sandybridge */
127 bridge_type |= 0x20;
128 }
129 writel(bridge_type, MCHBAR_REG(0x5f10));
130
131 /*
132 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
133 * that BIOS has initialized memory and power management
134 */
135 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1);
136 debug("Set BIOS_RESET_CPL\n");
137
138 /* Configure turbo power limits 1ms after reset complete bit */
139 mdelay(1);
140 set_power_limits(28);
141
142 /*
143 * CPUs with configurable TDP also need power limits set
144 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
145 */
Simon Glassb12689d2019-09-25 08:56:38 -0600146 if (cpu_ivybridge_config_tdp_levels()) {
Simon Glass61612ed2014-11-24 21:18:18 -0700147 msr_t msr = msr_read(MSR_PKG_POWER_LIMIT);
148
149 writel(msr.lo, MCHBAR_REG(0x59A0));
150 writel(msr.hi, MCHBAR_REG(0x59A4));
151 }
152
153 /* Set here before graphics PM init */
154 writel(0x00100001, MCHBAR_REG(0x5500));
155}
156
Simon Glass6b7f76d2016-01-17 16:11:27 -0700157static void sandybridge_setup_northbridge_bars(struct udevice *dev)
158{
159 /* Set up all hardcoded northbridge BARs */
160 debug("Setting up static registers\n");
161 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
162 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
Simon Glass55357302016-03-11 22:06:55 -0700163 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
164 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
Simon Glass6b7f76d2016-01-17 16:11:27 -0700165 /* 64MB - busses 0-63 */
166 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
167 dm_pci_write_config32(dev, PCIEXBAR + 4,
168 (0LL + DEFAULT_PCIEXBAR) >> 32);
169 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
170 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
171
172 /* Set C0000-FFFFF to access RAM on both reads and writes */
173 dm_pci_write_config8(dev, PAM0, 0x30);
174 dm_pci_write_config8(dev, PAM1, 0x33);
175 dm_pci_write_config8(dev, PAM2, 0x33);
176 dm_pci_write_config8(dev, PAM3, 0x33);
177 dm_pci_write_config8(dev, PAM4, 0x33);
178 dm_pci_write_config8(dev, PAM5, 0x33);
179 dm_pci_write_config8(dev, PAM6, 0x33);
180}
181
Simon Glasse7ceeef2019-02-16 20:24:57 -0700182/**
183 * sandybridge_init_iommu() - Set up IOMMU so that azalia can be used
184 *
185 * It is not obvious where these values come from. They may be undocumented.
186 */
187static void sandybridge_init_iommu(struct udevice *dev)
188{
189 u32 capid0_a;
190
191 dm_pci_read_config32(dev, 0xe4, &capid0_a);
192 if (capid0_a & (1 << 23)) {
193 log_debug("capid0_a not needed\n");
194 return;
195 }
196
197 /* setup BARs */
198 writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404));
199 writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400));
200 writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414));
201 writel(IOMMU_BASE2 | 1, MCHBAR_REG(0x5410));
202
203 /* lock policies */
204 writel(0x80000000, IOMMU_BASE1 + 0xff0);
205
206 /* Enable azalia sound */
207 writel(0x20000000, IOMMU_BASE2 + 0xff0);
208 writel(0xa0000000, IOMMU_BASE2 + 0xff0);
209}
210
Simon Glass4fa56b12016-01-17 16:11:31 -0700211static int bd82x6x_northbridge_early_init(struct udevice *dev)
Simon Glass6b7f76d2016-01-17 16:11:27 -0700212{
213 const int chipset_type = SANDYBRIDGE_MOBILE;
214 u32 capid0_a;
215 u8 reg8;
216
Simon Glass6b7f76d2016-01-17 16:11:27 -0700217 /* Device ID Override Enable should be done very early */
218 dm_pci_read_config32(dev, 0xe4, &capid0_a);
219 if (capid0_a & (1 << 10)) {
220 dm_pci_read_config8(dev, 0xf3, &reg8);
221 reg8 &= ~7; /* Clear 2:0 */
222
223 if (chipset_type == SANDYBRIDGE_MOBILE)
224 reg8 |= 1; /* Set bit 0 */
225
226 dm_pci_write_config8(dev, 0xf3, reg8);
227 }
228
229 sandybridge_setup_northbridge_bars(dev);
230
Simon Glasse7ceeef2019-02-16 20:24:57 -0700231 /* Setup IOMMU BARs */
232 sandybridge_init_iommu(dev);
233
Simon Glass6b7f76d2016-01-17 16:11:27 -0700234 /* Device Enable */
235 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
236
237 return 0;
238}
239
Simon Glass4fa56b12016-01-17 16:11:31 -0700240static int bd82x6x_northbridge_probe(struct udevice *dev)
241{
Simon Glass11f76a72016-01-17 16:11:54 -0700242 int rev;
243
Simon Glass4fa56b12016-01-17 16:11:31 -0700244 if (!(gd->flags & GD_FLG_RELOC))
245 return bd82x6x_northbridge_early_init(dev);
246
Simon Glass11f76a72016-01-17 16:11:54 -0700247 rev = bridge_silicon_revision(dev);
248 northbridge_init(dev, rev);
Simon Glass4fa56b12016-01-17 16:11:31 -0700249
250 return 0;
251}
252
Simon Glass6b7f76d2016-01-17 16:11:27 -0700253static const struct udevice_id bd82x6x_northbridge_ids[] = {
254 { .compatible = "intel,bd82x6x-northbridge" },
255 { }
256};
257
258U_BOOT_DRIVER(bd82x6x_northbridge_drv) = {
259 .name = "bd82x6x_northbridge",
260 .id = UCLASS_NORTHBRIDGE,
261 .of_match = bd82x6x_northbridge_ids,
262 .probe = bd82x6x_northbridge_probe,
263};