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git01.mediatek.com / filogic / uboot / 93f6bc229977240834992f3b1f25f1d593ab810c / . / arch / arm / dts / imx6qdl-aristainetos2b.dtsi
blob: 7d92ea2af7e409565ee200d0a0ac61955a9f2743 [file] [log] [blame]
Heiko Schocher57c4aad2019-12-01 11:23:30 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0)
2/*
3 * support for the imx6 based aristainetos2b board
4 *
5 * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
6 * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
7 *
8 */
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/clock/imx6qdl-clock.h>
11
12#include "imx6qdl-aristainetos2-common.dtsi"
13
14/ {
15 leds {
16 compatible = "gpio-leds";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_gpio>;
19
20 LED_blue {
21 label = "led_blue";
22 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
23 };
24
25 LED_green {
26 label = "led_green";
27 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
28 };
29
30 LED_red {
31 label = "led_red";
32 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
33 };
34
35 LED_yellow {
36 label = "led_yellow";
37 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
38 };
39
40 LED_ena {
41 label = "led_ena";
42 gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
43 };
44 };
45};
46
47&ecspi1 {
48 fsl,spi-num-chipselects = <3>;
49 cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
50 &gpio4 10 GPIO_ACTIVE_HIGH
51 &gpio4 11 GPIO_ACTIVE_HIGH>;
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_ecspi1>;
54 status = "okay";
55 pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
56 pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
57
58 flash: m25p80@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "micron,n25q128a11", "jedec,spi-nor";
62 spi-max-frequency = <20000000>;
63 reg = <0>;
64 };
65};
66
67&ecspi4 {
68 fsl,spi-num-chipselects = <2>;
69 cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ecspi4>;
72 status = "okay";
73};
74
75&i2c1 {
76 tpm@20 {
77 compatible = "infineon,slb9645tt";
78 reg = <0x20>;
79 };
80};
81
82&gpio7 {
83 sd2_driver_ena {
84 gpio-hog;
85 output-high;
86 gpios = <8 GPIO_ACTIVE_HIGH>;
87 };
88};
89
90&gpmi {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_gpmi_nand>;
93 status = "okay";
94};
95
96&can1 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_flexcan1>;
99 status = "okay";
100};
101
102&can2 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_flexcan2>;
105 status = "okay";
106};
107
108&usdhc1 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_usdhc1>;
111 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
112 wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
113 no-1-8-v;
114 status = "okay";
115};
116
117&usdhc2 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_usdhc2>;
120 /*
121 * comment out this line to make the WiFi Eval-Module work in
122 * SD-Slot2, and add line:
123 * broken-cd;
124 * causes 6% CPU load if no WiFi module installed (polling)
125 */
126 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
127 wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
128 no-1-8-v;
129 status = "okay";
130};
131
132&iomuxc {
133 pinctrl_ecspi1: ecspi1grp {
134 fsl,pins = <
135 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
136 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
137 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
138 /* SS0# */
139 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
140 /* SS1# */
141 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
142 /* SS2# */
143 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
144 /* WP pin NOR Flash */
145 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
146 /* Flash nReset */
147 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
148 >;
149 };
150
151 pinctrl_ecspi4: ecspi4grp {
152 fsl,pins = <
153 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
154 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
155 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
156 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
157 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
158 >;
159 };
160
161 pinctrl_gpio: gpiogrp {
162 fsl,pins = <
163 /* led enable */
164 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
165 /* LCD power enable */
166 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
167 /* led yellow */
168 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
169 /* led red */
170 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
171 /* led green */
172 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
173 /* led blue */
174 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
175 /* Profibus IRQ */
176 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
177 /* FPGA IRQ currently unused*/
178 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
179 /* Display reset because of clock failure */
180 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
181 /* spi bus #2 SS driver enable */
182 MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
183 /* RST_LOC# PHY reset input (has pull-down!)*/
184 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
185 /* Touchscreen IRQ */
186 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
187 /* PCIe reset */
188 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
189 /* make sure pin is GPIO and not ENET_REF_CLK */
190 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
191 /* SD2 level shifter output enable / SD2 Reset# */
192 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
193 >;
194 };
195
196 pinctrl_gpmi_nand: gpmi-nand {
197 fsl,pins = <
198 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
199 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
200 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
201 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
202 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
203 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
204 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
205 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
206 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
207 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
208 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
209 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
210 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
211 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
212 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
213 >;
214 };
215
216 pinctrl_flexcan1: flexcan1grp {
217 fsl,pins = <
218 MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
219 MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
220 >;
221 };
222
223 pinctrl_flexcan2: flexcan2grp {
224 fsl,pins = <
225 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
226 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
227 >;
228 };
229
230 pinctrl_usbotg: usbotggrp {
231 fsl,pins = <
232 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
233 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
234 >;
235 };
236
237 pinctrl_usdhc1: usdhc1grp {
238 fsl,pins = <
239 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
240 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
241 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
242 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
243 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
244 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
245 /* SD1 card detect input */
246 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
247 /* SD1 write protect input */
248 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
249 >;
250 };
251
252 pinctrl_usdhc2: usdhc2grp {
253 fsl,pins = <
254 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
255 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
256 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
257 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
258 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
259 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
260 /* SD2 card detect input */
261 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
262 /* SD2 write protect input */
263 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
264 >;
265 };
266};