TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 3 | * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <config.h> |
Peter Tyser | 6294850 | 2008-11-03 09:30:59 -0600 | [diff] [blame] | 25 | #include <timestamp.h> |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 26 | #include "version.h" |
| 27 | |
| 28 | #ifndef CONFIG_IDENT_STRING |
| 29 | #define CONFIG_IDENT_STRING "" |
| 30 | #endif |
| 31 | |
| 32 | /* last three long word reserved for cache status */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) |
| 34 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) |
| 35 | #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 36 | |
| 37 | #define _START _start |
| 38 | #define _FAULT _fault |
| 39 | |
| 40 | #define SAVE_ALL \ |
| 41 | move.w #0x2700,%sr; /* disable intrs */ \ |
| 42 | subl #60,%sp; /* space for 15 regs */ \ |
| 43 | moveml %d0-%d7/%a0-%a6,%sp@; |
| 44 | |
| 45 | #define RESTORE_ALL \ |
| 46 | moveml %sp@,%d0-%d7/%a0-%a6; \ |
| 47 | addl #60,%sp; /* space for 15 regs */ \ |
| 48 | rte; |
| 49 | |
| 50 | .text |
| 51 | /* |
| 52 | * Vector table. This is used for initial platform startup. |
| 53 | * These vectors are to catch any un-intended traps. |
| 54 | */ |
| 55 | _vectors: |
| 56 | |
| 57 | INITSP: .long 0x00000000 /* Initial SP */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 58 | INITPC: .long _START /* Initial PC */ |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 59 | vector02: .long _FAULT /* Access Error */ |
| 60 | vector03: .long _FAULT /* Address Error */ |
| 61 | vector04: .long _FAULT /* Illegal Instruction */ |
| 62 | vector05: .long _FAULT /* Reserved */ |
| 63 | vector06: .long _FAULT /* Reserved */ |
| 64 | vector07: .long _FAULT /* Reserved */ |
| 65 | vector08: .long _FAULT /* Privilege Violation */ |
| 66 | vector09: .long _FAULT /* Trace */ |
| 67 | vector0A: .long _FAULT /* Unimplemented A-Line */ |
| 68 | vector0B: .long _FAULT /* Unimplemented F-Line */ |
| 69 | vector0C: .long _FAULT /* Debug Interrupt */ |
| 70 | vector0D: .long _FAULT /* Reserved */ |
| 71 | vector0E: .long _FAULT /* Format Error */ |
| 72 | vector0F: .long _FAULT /* Unitialized Int. */ |
| 73 | |
| 74 | /* Reserved */ |
| 75 | vector10_17: |
| 76 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 77 | |
| 78 | vector18: .long _FAULT /* Spurious Interrupt */ |
| 79 | vector19: .long _FAULT /* Autovector Level 1 */ |
| 80 | vector1A: .long _FAULT /* Autovector Level 2 */ |
| 81 | vector1B: .long _FAULT /* Autovector Level 3 */ |
| 82 | vector1C: .long _FAULT /* Autovector Level 4 */ |
| 83 | vector1D: .long _FAULT /* Autovector Level 5 */ |
| 84 | vector1E: .long _FAULT /* Autovector Level 6 */ |
| 85 | vector1F: .long _FAULT /* Autovector Level 7 */ |
| 86 | |
| 87 | /* TRAP #0 - #15 */ |
| 88 | vector20_2F: |
| 89 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 90 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 91 | |
| 92 | /* Reserved */ |
| 93 | vector30_3F: |
| 94 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 95 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 96 | |
| 97 | vector64_127: |
| 98 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 99 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 100 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 101 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 102 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 103 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 104 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 105 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 106 | |
| 107 | vector128_191: |
| 108 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 109 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 110 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 111 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 112 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 113 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 114 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 115 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 116 | |
| 117 | vector192_255: |
| 118 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 119 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 120 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 121 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 122 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 123 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 124 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 125 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 126 | |
| 127 | .text |
| 128 | |
| 129 | .globl _start |
| 130 | _start: |
| 131 | nop |
| 132 | nop |
| 133 | move.w #0x2700,%sr /* Mask off Interrupt */ |
| 134 | |
| 135 | /* Set vector base register at the beginning of the Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | move.l #CONFIG_SYS_FLASH_BASE, %d0 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 137 | movec %d0, %VBR |
| 138 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 140 | movec %d0, %RAMBAR0 |
| 141 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 143 | movec %d0, %RAMBAR1 |
| 144 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 145 | move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 146 | move.c %d0, %MBAR |
| 147 | |
| 148 | /* invalidate and disable cache */ |
| 149 | move.l #0x01040100, %d0 /* Invalidate cache cmd */ |
| 150 | movec %d0, %CACR /* Invalidate cache */ |
| 151 | move.l #0, %d0 |
| 152 | movec %d0, %ACR0 |
| 153 | movec %d0, %ACR1 |
| 154 | movec %d0, %ACR2 |
| 155 | movec %d0, %ACR3 |
| 156 | |
| 157 | /* initialize general use internal ram */ |
| 158 | move.l #0, %d0 |
| 159 | move.l #(ICACHE_STATUS), %a1 /* icache */ |
| 160 | move.l #(DCACHE_STATUS), %a2 /* icache */ |
| 161 | move.l #(CACR_STATUS), %a3 /* CACR */ |
| 162 | move.l %d0, (%a1) |
| 163 | move.l %d0, (%a2) |
| 164 | move.l %d0, (%a3) |
| 165 | |
| 166 | /* set stackpointer to end of internal ram to get some stackspace for the |
| 167 | first c-code */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 169 | clr.l %sp@- |
| 170 | |
| 171 | move.l #__got_start, %a5 /* put relocation table address to a5 */ |
| 172 | |
| 173 | bsr cpu_init_f /* run low-level CPU init code (from flash) */ |
| 174 | bsr board_init_f /* run low-level board init code (from flash) */ |
| 175 | |
| 176 | /* board_init_f() does not return */ |
| 177 | |
| 178 | /*------------------------------------------------------------------------------*/ |
| 179 | |
| 180 | /* |
| 181 | * void relocate_code (addr_sp, gd, addr_moni) |
| 182 | * |
| 183 | * This "function" does not return, instead it continues in RAM |
| 184 | * after relocating the monitor code. |
| 185 | * |
| 186 | * r3 = dest |
| 187 | * r4 = src |
| 188 | * r5 = length in bytes |
| 189 | * r6 = cachelinesize |
| 190 | */ |
| 191 | .globl relocate_code |
| 192 | relocate_code: |
| 193 | link.w %a6,#0 |
| 194 | move.l 8(%a6), %sp /* set new stack pointer */ |
| 195 | |
| 196 | move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ |
| 197 | move.l 16(%a6), %a0 /* Save copy of Destination Address */ |
| 198 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 199 | move.l #CONFIG_SYS_MONITOR_BASE, %a1 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 200 | move.l #__init_end, %a2 |
| 201 | move.l %a0, %a3 |
| 202 | |
| 203 | /* copy the code to RAM */ |
| 204 | 1: |
| 205 | move.l (%a1)+, (%a3)+ |
| 206 | cmp.l %a1,%a2 |
| 207 | bgt.s 1b |
| 208 | |
| 209 | /* |
| 210 | * We are done. Do not return, instead branch to second part of board |
| 211 | * initialization, now running from RAM. |
| 212 | */ |
| 213 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 215 | jmp (%a1) |
| 216 | |
| 217 | in_ram: |
| 218 | |
| 219 | clear_bss: |
| 220 | /* |
| 221 | * Now clear BSS segment |
| 222 | */ |
| 223 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 224 | add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 225 | move.l %a0, %d1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 227 | 6: |
| 228 | clr.l (%a1)+ |
| 229 | cmp.l %a1,%d1 |
| 230 | bgt.s 6b |
| 231 | |
| 232 | /* |
| 233 | * fix got table in RAM |
| 234 | */ |
| 235 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 236 | add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 237 | move.l %a1,%a5 /* * fix got pointer register a5 */ |
| 238 | |
| 239 | move.l %a0, %a2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 240 | add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 241 | |
| 242 | 7: |
| 243 | move.l (%a1),%d1 |
| 244 | sub.l #_start,%d1 |
| 245 | add.l %a0,%d1 |
| 246 | move.l %d1,(%a1)+ |
| 247 | cmp.l %a2, %a1 |
| 248 | bne 7b |
| 249 | |
| 250 | /* calculate relative jump to board_init_r in ram */ |
| 251 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 252 | add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 253 | |
| 254 | /* set parameters for board_init_r */ |
| 255 | move.l %a0,-(%sp) /* dest_addr */ |
| 256 | move.l %d0,-(%sp) /* gd */ |
| 257 | jsr (%a1) |
| 258 | |
| 259 | /*------------------------------------------------------------------------------*/ |
| 260 | /* exception code */ |
| 261 | .globl _fault |
| 262 | _fault: |
TsiChung Liew | 160e11e | 2008-06-18 19:12:13 -0500 | [diff] [blame] | 263 | bra _fault |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 264 | .globl _exc_handler |
| 265 | |
| 266 | _exc_handler: |
| 267 | SAVE_ALL |
| 268 | movel %sp,%sp@- |
| 269 | bsr exc_handler |
| 270 | addql #4,%sp |
| 271 | RESTORE_ALL |
| 272 | |
| 273 | .globl _int_handler |
| 274 | _int_handler: |
| 275 | SAVE_ALL |
| 276 | movel %sp,%sp@- |
| 277 | bsr int_handler |
| 278 | addql #4,%sp |
| 279 | RESTORE_ALL |
| 280 | |
| 281 | /*------------------------------------------------------------------------------*/ |
| 282 | /* cache functions */ |
| 283 | .globl icache_enable |
| 284 | icache_enable: |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 285 | move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 286 | movec %d0, %ACR2 /* Enable cache */ |
| 287 | |
| 288 | move.l #0x020C8100, %d0 /* Setup cache mask */ |
| 289 | movec %d0, %CACR /* Enable cache */ |
| 290 | nop |
| 291 | |
| 292 | move.l #(ICACHE_STATUS), %a1 |
| 293 | moveq #1, %d0 |
| 294 | move.l %d0, (%a1) |
| 295 | rts |
| 296 | |
| 297 | .globl icache_disable |
| 298 | icache_disable: |
| 299 | move.l #0x000C8100, %d0 /* Setup cache mask */ |
| 300 | movec %d0, %CACR /* Disable cache */ |
| 301 | clr.l %d0 /* Setup cache mask */ |
| 302 | movec %d0, %ACR2 |
| 303 | movec %d0, %ACR3 |
| 304 | |
| 305 | move.l #(ICACHE_STATUS), %a1 |
| 306 | moveq #0, %d0 |
| 307 | move.l %d0, (%a1) |
| 308 | rts |
| 309 | |
| 310 | .globl icache_invalid |
| 311 | icache_invalid: |
| 312 | move.l #0x000C8100, %d0 /* Setup cache mask */ |
| 313 | movec %d0, %CACR /* Enable cache */ |
| 314 | rts |
| 315 | |
| 316 | .globl icache_status |
| 317 | icache_status: |
| 318 | move.l #(ICACHE_STATUS), %a1 |
| 319 | move.l (%a1), %d0 |
| 320 | rts |
| 321 | |
| 322 | .globl dcache_enable |
| 323 | dcache_enable: |
| 324 | bsr icache_disable |
| 325 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 326 | move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 327 | movec %d0, %ACR0 /* Enable cache */ |
| 328 | |
| 329 | move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ |
| 330 | movec %d0, %CACR /* Invalidate cache */ |
| 331 | |
| 332 | move.l #(DCACHE_STATUS), %a1 |
| 333 | moveq #1, %d0 |
| 334 | move.l %d0, (%a1) |
| 335 | rts |
| 336 | |
| 337 | .globl dcache_disable |
| 338 | dcache_disable: |
| 339 | move.l #0xA30C8100, %d0 /* Setup cache mask */ |
| 340 | movec %d0, %CACR /* Disable cache */ |
| 341 | clr.l %d0 /* Setup cache mask */ |
| 342 | movec %d0, %ACR0 |
| 343 | movec %d0, %ACR1 |
| 344 | |
| 345 | move.l #(DCACHE_STATUS), %a1 |
| 346 | moveq #0, %d0 |
| 347 | move.l %d0, (%a1) |
| 348 | rts |
| 349 | |
| 350 | .globl dcache_status |
| 351 | dcache_status: |
| 352 | move.l #(DCACHE_STATUS), %a1 |
| 353 | move.l (%a1), %d0 |
| 354 | rts |
| 355 | |
| 356 | /*------------------------------------------------------------------------------*/ |
| 357 | |
| 358 | .globl version_string |
| 359 | version_string: |
| 360 | .ascii U_BOOT_VERSION |
Peter Tyser | 6294850 | 2008-11-03 09:30:59 -0600 | [diff] [blame] | 361 | .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" |
TsiChungLiew | 8999e6b | 2008-01-15 13:37:34 -0600 | [diff] [blame] | 362 | .ascii CONFIG_IDENT_STRING, "\0" |
TsiChung Liew | 9d636e9 | 2008-03-28 08:47:45 -0500 | [diff] [blame] | 363 | .align 4 |