| TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Pulse Width Modulation Memory Map |
| 3 | * |
| 4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __ATA_H__ |
| 11 | #define __ATA_H__ |
| 12 | |
| 13 | /* Pulse Width Modulation (PWM) */ |
| 14 | typedef struct pwm_ctrl { |
| 15 | #ifdef CONFIG_M5272 |
| 16 | u8 cr0; |
| 17 | u8 res1[3]; |
| 18 | u8 cr1; |
| 19 | u8 res2[3]; |
| 20 | u8 cr2; |
| 21 | u8 res3[7]; |
| 22 | u8 pwr0; |
| 23 | u8 res4[3]; |
| 24 | u8 pwr1; |
| 25 | u8 res5[3]; |
| 26 | u8 pwr2; |
| 27 | u8 res6[7]; |
| 28 | #else |
| 29 | u8 en; /* 0x00 PWM Enable */ |
| 30 | u8 pol; /* 0x01 Polarity */ |
| 31 | u8 clk; /* 0x02 Clock Select */ |
| 32 | u8 prclk; /* 0x03 Prescale Clock Select */ |
| 33 | u8 cae; /* 0x04 Center Align Enable */ |
| 34 | u8 ctl; /* 0x05 Control */ |
| 35 | u16 res1; /* 0x06 - 0x07 */ |
| 36 | u8 scla; /* 0x08 Scale A */ |
| 37 | u8 sclb; /* 0x09 Scale B */ |
| 38 | u16 res2; /* 0x0A - 0x0B */ |
| 39 | #ifdef CONFIG_M5275 |
| 40 | u8 cnt[4]; /* 0x0C Channel n Counter */ |
| 41 | u16 res3; /* 0x10 - 0x11 */ |
| 42 | u8 per[4]; /* 0x14 Channel n Period */ |
| 43 | u16 res4; /* 0x16 - 0x17 */ |
| 44 | u8 dty[4]; /* 0x18 Channel n Duty */ |
| 45 | #else |
| 46 | u8 cnt[8]; /* 0x0C Channel n Counter */ |
| 47 | u8 per[8]; /* 0x14 Channel n Period */ |
| 48 | u8 dty[8]; /* 0x1C Channel n Duty */ |
| 49 | u8 sdn; /* 0x24 Shutdown */ |
| 50 | u8 res3[3]; /* 0x25 - 0x27 */ |
| 51 | #endif /* CONFIG_M5275 */ |
| 52 | #endif /* CONFIG_M5272 */ |
| 53 | } pwm_t; |
| 54 | |
| 55 | #ifdef CONFIG_M5272 |
| 56 | |
| 57 | #define PWM_CR_EN (0x80) |
| 58 | #define PWM_CR_FRC1 (0x40) |
| 59 | #define PWM_CR_LVL (0x20) |
| 60 | #define PWM_CR_CLKSEL(x) ((x) & 0x0F) |
| 61 | #define PWM_CR_CLKSEL_MASK (0xF0) |
| 62 | |
| 63 | #else |
| 64 | |
| 65 | #define PWM_EN_PWMEn(x) (1 << ((x) & 0x07)) |
| 66 | #define PWM_EN_PWMEn_MASK (0xF0) |
| 67 | |
| 68 | #define PWM_POL_PPOLn(x) (1 << ((x) & 0x07)) |
| 69 | #define PWM_POL_PPOLn_MASK (0xF0) |
| 70 | |
| 71 | #define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) |
| 72 | #define PWM_CLK_PCLKn_MASK (0xF0) |
| 73 | |
| 74 | #define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4) |
| 75 | #define PWM_PRCLK_PCKB_MASK (0x8F) |
| 76 | #define PWM_PRCLK_PCKA(x) ((x) & 0x07) |
| 77 | #define PWM_PRCLK_PCKA_MASK (0xF8) |
| 78 | |
| 79 | #define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) |
| 80 | #define PWM_CLK_PCLKn_MASK (0xF0) |
| 81 | |
| 82 | #define PWM_CTL_CON67 (0x80) |
| 83 | #define PWM_CTL_CON45 (0x40) |
| 84 | #define PWM_CTL_CON23 (0x20) |
| 85 | #define PWM_CTL_CON01 (0x10) |
| 86 | #define PWM_CTL_PSWAR (0x08) |
| 87 | #define PWM_CTL_PFRZ (0x04) |
| 88 | |
| 89 | #define PWM_SDN_IF (0x80) |
| 90 | #define PWM_SDN_IE (0x40) |
| 91 | #define PWM_SDN_RESTART (0x20) |
| 92 | #define PWM_SDN_LVL (0x10) |
| 93 | #define PWM_SDN_PWM7IN (0x04) |
| 94 | #define PWM_SDN_PWM7IL (0x02) |
| 95 | #define PWM_SDN_SDNEN (0x01) |
| 96 | |
| 97 | #endif /* CONFIG_M5272 */ |
| 98 | |
| 99 | #endif /* __ATA_H__ */ |