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git01.mediatek.com / filogic / uboot / 9397fbeb94cbcab093f0d214ea4d5c4141815ecd / . / arch / arm / mach-uniphier / ph1-pro4 / pll_init.c
blob: d693368816c8670fd6bc132e72edd25974ccdd55 [file] [log] [blame]
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]1/*
Masahiro Yamada663a23f2015-05-29 17:30:00 +0900[diff] [blame]2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Masahiro Yamada663a23f2015-05-29 17:30:00 +0900[diff] [blame]8#include <linux/io.h>
Masahiro Yamada95387e22015-02-27 02:26:44 +0900[diff] [blame]9#include <mach/sc-regs.h>
10#include <mach/sg-regs.h>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]11
12#undef DPLL_SSC_RATE_1PER
13
Masahiro Yamadacfd171f2015-01-21 15:06:06 +0900[diff] [blame]14static void dpll_init(void)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]15{
16 u32 tmp;
17
18 /*
19 * Set Frequency
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT ( DPLLCTRL.bit[29:20] )
22 */
23 tmp = readl(SC_DPLLCTRL);
24 tmp &= ~(0x000f0000);
25#if CONFIG_DDR_FREQ == 1600
26 tmp |= 0x000c0000;
27#elif CONFIG_DDR_FREQ == 1333
28 tmp |= 0x000d0000;
29#else
30# error "Unsupported frequency"
31#endif
32
33 /*
34 * Set Moduration rate
35 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
36 */
37#if defined(DPLL_SSC_RATE_1PER)
38 tmp &= ~0x00008000;
39#else
40 tmp |= 0x00008000;
41#endif
42 writel(tmp, SC_DPLLCTRL);
43
44 tmp = readl(SC_DPLLCTRL2);
45 tmp |= SC_DPLLCTRL2_NRSTDS;
46 writel(tmp, SC_DPLLCTRL2);
47}
48
Masahiro Yamadacfd171f2015-01-21 15:06:06 +0900[diff] [blame]49static void vpll_init(void)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]50{
51 u32 tmp, clk_mode_axosel;
52
53 /* Set VPLL27A & VPLL27B */
54 tmp = readl(SG_PINMON0);
55 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
56
57#if defined(CONFIG_MACH_PH1_PRO4)
58 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
59 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
60 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
61 return;
62#endif
63
64 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
65 tmp = readl(SC_VPLL27ACTRL);
66 tmp |= 0x00000001;
67 writel(tmp, SC_VPLL27ACTRL);
68 tmp = readl(SC_VPLL27BCTRL);
69 tmp |= 0x00000001;
70 writel(tmp, SC_VPLL27BCTRL);
71
72 /* Unset VPLA_K_LD and VPLB_K_LD bit */
73 tmp = readl(SC_VPLL27ACTRL3);
74 tmp &= ~0x10000000;
75 writel(tmp, SC_VPLL27ACTRL3);
76 tmp = readl(SC_VPLL27BCTRL3);
77 tmp &= ~0x10000000;
78 writel(tmp, SC_VPLL27BCTRL3);
79
80 /* Set VPLA_M and VPLB_M to 0x20 */
81 tmp = readl(SC_VPLL27ACTRL2);
82 tmp &= ~0x0000007f;
83 tmp |= 0x00000020;
84 writel(tmp, SC_VPLL27ACTRL2);
85 tmp = readl(SC_VPLL27BCTRL2);
86 tmp &= ~0x0000007f;
87 tmp |= 0x00000020;
88 writel(tmp, SC_VPLL27BCTRL2);
89
90 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
91 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
92 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
93 tmp = readl(SC_VPLL27ACTRL3);
94 tmp &= ~0x000fffff;
95 tmp |= 0x00066666;
96 writel(tmp, SC_VPLL27ACTRL3);
97 tmp = readl(SC_VPLL27BCTRL3);
98 tmp &= ~0x000fffff;
99 tmp |= 0x00066666;
100 writel(tmp, SC_VPLL27BCTRL3);
101 } else {
102 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
103 tmp = readl(SC_VPLL27ACTRL3);
104 tmp &= ~0x000fffff;
105 tmp |= 0x000f5800;
106 writel(tmp, SC_VPLL27ACTRL3);
107 tmp = readl(SC_VPLL27BCTRL3);
108 tmp &= ~0x000fffff;
109 tmp |= 0x000f5800;
110 writel(tmp, SC_VPLL27BCTRL3);
111 }
112
113 /* wait 1 usec */
114 udelay(1);
115
116 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
117 tmp = readl(SC_VPLL27ACTRL3);
118 tmp |= 0x10000000;
119 writel(tmp, SC_VPLL27ACTRL3);
120 tmp = readl(SC_VPLL27BCTRL3);
121 tmp |= 0x10000000;
122 writel(tmp, SC_VPLL27BCTRL3);
123
124 /* Unset VPLA_SNRST and VPLB_SNRST bit */
125 tmp = readl(SC_VPLL27ACTRL2);
126 tmp |= 0x10000000;
127 writel(tmp, SC_VPLL27ACTRL2);
128 tmp = readl(SC_VPLL27BCTRL2);
129 tmp |= 0x10000000;
130 writel(tmp, SC_VPLL27BCTRL2);
131
132 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
133 tmp = readl(SC_VPLL27ACTRL);
134 tmp &= ~0x00000001;
135 writel(tmp, SC_VPLL27ACTRL);
136 tmp = readl(SC_VPLL27BCTRL);
137 tmp &= ~0x00000001;
138 writel(tmp, SC_VPLL27BCTRL);
139}
140
141void pll_init(void)
142{
143 dpll_init();
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]144 vpll_init();
145
146 /*
147 * Wait 500 usec until dpll get stable
148 * We wait 1 usec in vpll_init() so 1 usec can be saved here.
149 */
150 udelay(499);
151}