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Stelian Pop69c925f2008-05-08 18:52:23 +02001/*
2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h]
3 *
4 * (C) 2007 Atmel Corporation.
Reinhard Meyerd77e32a2010-11-19 10:05:01 +01005 * (C) Copyright 2010
6 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
Stelian Pop69c925f2008-05-08 18:52:23 +02007 *
Reinhard Meyerd77e32a2010-11-19 10:05:01 +01008 * Definitions for the SoC:
9 * AT91SAM9263
Stelian Pop69c925f2008-05-08 18:52:23 +020010 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop69c925f2008-05-08 18:52:23 +020012 */
13
14#ifndef AT91SAM9263_H
15#define AT91SAM9263_H
16
17/*
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010018 * defines to be used in other places
Stelian Pop69c925f2008-05-08 18:52:23 +020019 */
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010020#define CONFIG_AT91FAMILY /* it's a member of AT91 */
Stelian Pop69c925f2008-05-08 18:52:23 +020021
22/*
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010023 * Peripheral identifiers/interrupts.
Stelian Pop69c925f2008-05-08 18:52:23 +020024 */
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010025#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
26#define ATMEL_ID_SYS 1 /* System Peripherals */
27#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */
28#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */
29#define ATMEL_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
30/* Reserved: 5 */
31/* Reserved: 6 */
32#define ATMEL_ID_USART0 7 /* USART 0 */
33#define ATMEL_ID_USART1 8 /* USART 1 */
34#define ATMEL_ID_USART2 9 /* USART 2 */
35#define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */
36#define ATMEL_ID_MCI1 11 /* Multimedia Card Interface 1 */
37#define ATMEL_ID_CAN 12 /* CAN */
38#define ATMEL_ID_TWI 13 /* Two-Wire Interface */
39#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
40#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
41#define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */
42#define ATMEL_ID_SSC1 17 /* Serial Synchronous Controller 1 */
43#define ATMEL_ID_AC97C 18 /* AC97 Controller */
44#define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
45#define ATMEL_ID_PWMC 20 /* Pulse Width Modulation Controller */
46#define ATMEL_ID_EMAC 21 /* Ethernet */
47/* Reserved: 22 */
48#define ATMEL_ID_2DGE 23 /* 2D Graphic Engine */
49#define ATMEL_ID_UDP 24 /* USB Device Port */
50#define ATMEL_ID_ISI 25 /* Image Sensor Interface */
51#define ATMEL_ID_LCDC 26 /* LCD Controller */
52#define ATMEL_ID_DMA 27 /* DMA Controller */
53/* Reserved: 28 */
54#define ATMEL_ID_UHP 29 /* USB Host port */
55#define ATMEL_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
56#define ATMEL_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
Stelian Pop69c925f2008-05-08 18:52:23 +020057
58/*
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010059 * User Peripherals physical base addresses.
Stelian Pop69c925f2008-05-08 18:52:23 +020060 */
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010061#define ATMEL_BASE_UDP 0xfff78000
62#define ATMEL_BASE_TCB0 0xfff7c000
63#define ATMEL_BASE_TC0 0xfff7c000
64#define ATMEL_BASE_TC1 0xfff7c040
65#define ATMEL_BASE_TC2 0xfff7c080
66#define ATMEL_BASE_MCI0 0xfff80000
67#define ATMEL_BASE_MCI1 0xfff84000
68#define ATMEL_BASE_TWI 0xfff88000
69#define ATMEL_BASE_USART0 0xfff8c000
70#define ATMEL_BASE_USART1 0xfff90000
71#define ATMEL_BASE_USART2 0xfff94000
72#define ATMEL_BASE_SSC0 0xfff98000
73#define ATMEL_BASE_SSC1 0xfff9c000
74#define ATMEL_BASE_AC97C 0xfffa0000
75#define ATMEL_BASE_SPI0 0xfffa4000
76#define ATMEL_BASE_SPI1 0xfffa8000
77#define ATMEL_BASE_CAN 0xfffac000
78#define ATMEL_BASE_PWMC 0xfffb8000
79#define ATMEL_BASE_EMAC 0xfffbc000
80#define ATMEL_BASE_ISI 0xfffc4000
81#define ATMEL_BASE_2DGE 0xfffc8000
Stelian Pop69c925f2008-05-08 18:52:23 +020082
Reinhard Meyerd77e32a2010-11-19 10:05:01 +010083/*
84 * System Peripherals physical base addresses.
85 */
86#define ATMEL_BASE_ECC0 0xffffe000
87#define ATMEL_BASE_SDRAMC0 0xffffe200
88#define ATMEL_BASE_SMC0 0xffffe400
89#define ATMEL_BASE_ECC1 0xffffe600
90#define ATMEL_BASE_SDRAMC1 0xffffe800
91#define ATMEL_BASE_SMC1 0xffffea00
92#define ATMEL_BASE_MATRIX 0xffffec00
93#define ATMEL_BASE_CCFG 0xffffed10
94#define ATMEL_BASE_DBGU 0xffffee00
95#define ATMEL_BASE_AIC 0xfffff000
96#define ATMEL_BASE_PIOA 0xfffff200
97#define ATMEL_BASE_PIOB 0xfffff400
98#define ATMEL_BASE_PIOC 0xfffff600
99#define ATMEL_BASE_PIOD 0xfffff800
100#define ATMEL_BASE_PIOE 0xfffffa00
101#define ATMEL_BASE_PMC 0xfffffc00
102#define ATMEL_BASE_RSTC 0xfffffd00
103#define ATMEL_BASE_SHDWC 0xfffffd10
104#define ATMEL_BASE_RTT0 0xfffffd20
105#define ATMEL_BASE_PIT 0xfffffd30
106#define ATMEL_BASE_WDT 0xfffffd40
107#define ATMEL_BASE_RTT1 0xfffffd50
108#define ATMEL_BASE_GPBR 0xfffffd60
Jens Scharsig698ad062010-02-03 22:46:01 +0100109
Stelian Pop69c925f2008-05-08 18:52:23 +0200110/*
111 * Internal Memory.
112 */
Reinhard Meyerd77e32a2010-11-19 10:05:01 +0100113#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM 0 */
Stelian Pop69c925f2008-05-08 18:52:23 +0200114
Reinhard Meyerd77e32a2010-11-19 10:05:01 +0100115#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM */
Stelian Pop69c925f2008-05-08 18:52:23 +0200116
Reinhard Meyerd77e32a2010-11-19 10:05:01 +0100117#define ATMEL_BASE_SRAM1 0x00500000 /* Internal SRAM 1 */
Stelian Pop69c925f2008-05-08 18:52:23 +0200118
Reinhard Meyerd77e32a2010-11-19 10:05:01 +0100119#define ATMEL_BASE_LCDC 0x00700000 /* LCD Controller */
120#define ATMEL_BASE_DMAC 0x00800000 /* DMA Controller */
121#define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */
122
123/*
Xu, Hong4fae89c2011-06-10 21:31:25 +0000124 * External memory
125 */
126#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */
127#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */
128#define ATMEL_BASE_CS2 0x30000000
129#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */
130#define ATMEL_BASE_CS4 0x50000000
131#define ATMEL_BASE_CS5 0x60000000
132#define ATMEL_BASE_CS6 0x70000000
133#define ATMEL_BASE_CS7 0x80000000
134
Bo Shen568079a2015-02-04 15:53:01 +0800135/* Timer */
136#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
137
Xu, Hong4fae89c2011-06-10 21:31:25 +0000138/*
Reinhard Meyerd77e32a2010-11-19 10:05:01 +0100139 * Other misc defines
140 */
141#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
Eric Benard470a57b2011-06-06 22:48:27 +0000142#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
Xu, Hong4fae89c2011-06-10 21:31:25 +0000143#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
Stelian Pop69c925f2008-05-08 18:52:23 +0200144
Jean-Christophe PLAGNIOL-VILLARDb21aa662009-05-31 12:44:46 +0200145/*
146 * Cpu Name
147 */
Reinhard Meyerd77e32a2010-11-19 10:05:01 +0100148#define ATMEL_CPU_NAME "AT91SAM9263"
Stelian Pop69c925f2008-05-08 18:52:23 +0200149
150#endif