Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx ZynqMP SM-K26 rev1/B/A |
| 4 | * |
| 5 | * (C) Copyright 2020 - 2021, Xilinx, Inc. |
| 6 | * |
| 7 | * Michal Simek <michal.simek@amd.com> |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
| 12 | #include "zynqmp.dtsi" |
| 13 | #include "zynqmp-clk-ccf.dtsi" |
| 14 | #include <dt-bindings/input/input.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> |
| 16 | #include <dt-bindings/phy/phy.h> |
| 17 | #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> |
| 18 | |
| 19 | / { |
| 20 | model = "ZynqMP SM-K26 Rev1/B/A"; |
| 21 | compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", |
| 22 | "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", |
| 23 | "xlnx,zynqmp"; |
| 24 | |
| 25 | aliases { |
| 26 | i2c0 = &i2c0; |
| 27 | i2c1 = &i2c1; |
| 28 | mmc0 = &sdhci0; |
| 29 | mmc1 = &sdhci1; |
| 30 | nvmem0 = &eeprom; |
| 31 | nvmem1 = &eeprom_cc; |
| 32 | rtc0 = &rtc; |
| 33 | serial0 = &uart0; |
| 34 | serial1 = &uart1; |
| 35 | serial2 = &dcc; |
| 36 | spi0 = &qspi; |
| 37 | spi1 = &spi0; |
| 38 | spi2 = &spi1; |
| 39 | usb0 = &usb0; |
| 40 | usb1 = &usb1; |
| 41 | }; |
| 42 | |
| 43 | chosen { |
| 44 | bootargs = "earlycon"; |
| 45 | stdout-path = "serial1:115200n8"; |
| 46 | }; |
| 47 | |
| 48 | memory@0 { |
| 49 | device_type = "memory"; /* 4GB */ |
| 50 | reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
| 51 | }; |
| 52 | |
| 53 | reserved-memory { |
| 54 | #address-cells = <2>; |
| 55 | #size-cells = <2>; |
| 56 | ranges; |
| 57 | |
| 58 | pmu_region: pmu@7ff00000 { |
| 59 | reg = <0x0 0x7ff00000 0x0 0x100000>; |
| 60 | no-map; |
| 61 | }; |
| 62 | }; |
| 63 | |
| 64 | gpio-keys { |
| 65 | compatible = "gpio-keys"; |
| 66 | autorepeat; |
| 67 | key-fwuen { |
| 68 | label = "fwuen"; |
| 69 | gpios = <&gpio 12 GPIO_ACTIVE_LOW>; |
| 70 | linux,code = <BTN_MISC>; |
| 71 | wakeup-source; |
| 72 | autorepeat; |
| 73 | }; |
| 74 | }; |
| 75 | |
| 76 | leds { |
| 77 | compatible = "gpio-leds"; |
| 78 | ds35-led { |
| 79 | label = "heartbeat"; |
| 80 | gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; |
| 81 | linux,default-trigger = "heartbeat"; |
| 82 | }; |
| 83 | |
| 84 | ds36-led { |
| 85 | label = "vbus_det"; |
| 86 | gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; |
| 87 | default-state = "on"; |
| 88 | }; |
| 89 | }; |
| 90 | |
| 91 | ams { |
| 92 | compatible = "iio-hwmon"; |
| 93 | io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, |
| 94 | <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, |
| 95 | <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, |
| 96 | <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, |
| 97 | <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, |
| 98 | <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, |
| 99 | <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, |
| 100 | <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, |
| 101 | <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, |
| 102 | <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; |
| 103 | }; |
| 104 | }; |
| 105 | |
| 106 | &modepin_gpio { |
| 107 | label = "modepin"; |
| 108 | }; |
| 109 | |
| 110 | &uart1 { /* MIO36/MIO37 */ |
| 111 | status = "okay"; |
| 112 | }; |
| 113 | |
| 114 | &pinctrl0 { |
| 115 | status = "okay"; |
| 116 | pinctrl_sdhci0_default: sdhci0-default { |
| 117 | conf { |
| 118 | groups = "sdio0_0_grp"; |
| 119 | slew-rate = <SLEW_RATE_SLOW>; |
| 120 | power-source = <IO_STANDARD_LVCMOS18>; |
| 121 | bias-disable; |
| 122 | }; |
| 123 | |
| 124 | mux { |
| 125 | groups = "sdio0_0_grp"; |
| 126 | function = "sdio0"; |
| 127 | }; |
| 128 | }; |
| 129 | }; |
| 130 | |
| 131 | &qspi { /* MIO 0-5 - U143 */ |
| 132 | status = "okay"; |
| 133 | spi_flash: flash@0 { /* MT25QU512A */ |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 134 | compatible = "jedec,spi-nor"; /* 64MB */ |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 135 | reg = <0>; |
| 136 | spi-tx-bus-width = <4>; |
| 137 | spi-rx-bus-width = <4>; |
| 138 | spi-max-frequency = <40000000>; /* 40MHz */ |
| 139 | |
| 140 | partitions { |
| 141 | compatible = "fixed-partitions"; |
| 142 | #address-cells = <1>; |
| 143 | #size-cells = <1>; |
| 144 | |
| 145 | partition@0 { |
| 146 | label = "Image Selector"; |
| 147 | reg = <0x0 0x80000>; /* 512KB */ |
| 148 | read-only; |
| 149 | lock; |
| 150 | }; |
| 151 | partition@80000 { |
| 152 | label = "Image Selector Golden"; |
| 153 | reg = <0x80000 0x80000>; /* 512KB */ |
| 154 | read-only; |
| 155 | lock; |
| 156 | }; |
| 157 | partition@100000 { |
| 158 | label = "Persistent Register"; |
| 159 | reg = <0x100000 0x20000>; /* 128KB */ |
| 160 | }; |
| 161 | partition@120000 { |
| 162 | label = "Persistent Register Backup"; |
| 163 | reg = <0x120000 0x20000>; /* 128KB */ |
| 164 | }; |
| 165 | partition@140000 { |
| 166 | label = "Open_1"; |
| 167 | reg = <0x140000 0xC0000>; /* 768KB */ |
| 168 | }; |
| 169 | partition@200000 { |
| 170 | label = "Image A (FSBL, PMU, ATF, U-Boot)"; |
| 171 | reg = <0x200000 0xD00000>; /* 13MB */ |
| 172 | }; |
| 173 | partition@f00000 { |
| 174 | label = "ImgSel Image A Catch"; |
| 175 | reg = <0xF00000 0x80000>; /* 512KB */ |
| 176 | read-only; |
| 177 | lock; |
| 178 | }; |
| 179 | partition@f80000 { |
| 180 | label = "Image B (FSBL, PMU, ATF, U-Boot)"; |
| 181 | reg = <0xF80000 0xD00000>; /* 13MB */ |
| 182 | }; |
| 183 | partition@1c80000 { |
| 184 | label = "ImgSel Image B Catch"; |
| 185 | reg = <0x1C80000 0x80000>; /* 512KB */ |
| 186 | read-only; |
| 187 | lock; |
| 188 | }; |
| 189 | partition@1d00000 { |
| 190 | label = "Open_2"; |
| 191 | reg = <0x1D00000 0x100000>; /* 1MB */ |
| 192 | }; |
| 193 | partition@1e00000 { |
| 194 | label = "Recovery Image"; |
| 195 | reg = <0x1E00000 0x200000>; /* 2MB */ |
| 196 | read-only; |
| 197 | lock; |
| 198 | }; |
| 199 | partition@2000000 { |
| 200 | label = "Recovery Image Backup"; |
| 201 | reg = <0x2000000 0x200000>; /* 2MB */ |
| 202 | read-only; |
| 203 | lock; |
| 204 | }; |
| 205 | partition@2200000 { |
| 206 | label = "U-Boot storage variables"; |
| 207 | reg = <0x2200000 0x20000>; /* 128KB */ |
| 208 | }; |
| 209 | partition@2220000 { |
| 210 | label = "U-Boot storage variables backup"; |
| 211 | reg = <0x2220000 0x20000>; /* 128KB */ |
| 212 | }; |
| 213 | partition@2240000 { |
| 214 | label = "SHA256"; |
| 215 | reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ |
| 216 | read-only; |
| 217 | lock; |
| 218 | }; |
| 219 | partition@2280000 { |
| 220 | label = "Secure OS Storage"; |
| 221 | reg = <0x2280000 0x20000>; /* 128KB */ |
| 222 | }; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 223 | partition@22a0000 { |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 224 | label = "User"; |
Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 225 | reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ |
Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 226 | }; |
| 227 | }; |
| 228 | }; |
| 229 | }; |
| 230 | |
| 231 | &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ |
| 232 | status = "okay"; |
| 233 | pinctrl-names = "default"; |
| 234 | pinctrl-0 = <&pinctrl_sdhci0_default>; |
| 235 | non-removable; |
| 236 | disable-wp; |
| 237 | bus-width = <8>; |
| 238 | xlnx,mio-bank = <0>; |
| 239 | assigned-clock-rates = <187498123>; |
| 240 | }; |
| 241 | |
| 242 | &spi1 { /* MIO6, 9-11 */ |
| 243 | status = "okay"; |
| 244 | label = "TPM"; |
| 245 | num-cs = <1>; |
| 246 | tpm@0 { /* slm9670 - U144 */ |
| 247 | compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; |
| 248 | reg = <0>; |
| 249 | spi-max-frequency = <18500000>; |
| 250 | }; |
| 251 | }; |
| 252 | |
| 253 | &i2c1 { |
| 254 | status = "okay"; |
| 255 | bootph-all; |
| 256 | clock-frequency = <400000>; |
| 257 | scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 258 | sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| 259 | |
| 260 | eeprom: eeprom@50 { /* u46 - also at address 0x58 */ |
| 261 | bootph-all; |
| 262 | compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ |
| 263 | reg = <0x50>; |
| 264 | /* WP pin EE_WP_EN connected to slg7x644092@68 */ |
| 265 | }; |
| 266 | |
| 267 | eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ |
| 268 | bootph-all; |
| 269 | compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ |
| 270 | reg = <0x51>; |
| 271 | }; |
| 272 | |
| 273 | /* da9062@30 - u170 - also at address 0x31 */ |
| 274 | /* da9131@33 - u167 */ |
| 275 | da9131: pmic@33 { |
| 276 | compatible = "dlg,da9131"; |
| 277 | reg = <0x33>; |
| 278 | regulators { |
| 279 | da9131_buck1: buck1 { |
| 280 | regulator-name = "da9131_buck1"; |
| 281 | regulator-boot-on; |
| 282 | regulator-always-on; |
| 283 | }; |
| 284 | da9131_buck2: buck2 { |
| 285 | regulator-name = "da9131_buck2"; |
| 286 | regulator-boot-on; |
| 287 | regulator-always-on; |
| 288 | }; |
| 289 | }; |
| 290 | }; |
| 291 | |
| 292 | /* da9130@32 - u166 */ |
| 293 | da9130: pmic@32 { |
| 294 | compatible = "dlg,da9130"; |
| 295 | reg = <0x32>; |
| 296 | regulators { |
| 297 | da9130_buck1: buck1 { |
| 298 | regulator-name = "da9130_buck1"; |
| 299 | regulator-boot-on; |
| 300 | regulator-always-on; |
| 301 | }; |
| 302 | }; |
| 303 | }; |
| 304 | |
| 305 | /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ |
| 306 | /* |
| 307 | * stdp4320 - u27 FW has below two issues to be fixed in next board revision. |
| 308 | * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. |
| 309 | * Address conflict with slg7x644091@70 making both the devices NOT accessible. |
| 310 | * With the FW fix, stdp4320 should respond to address 0x73 only. |
| 311 | */ |
| 312 | /* slg7x644092@68 - u169 */ |
| 313 | /* Also connected via JA1C as C23/C24 */ |
| 314 | }; |
| 315 | |
| 316 | &gpio { |
| 317 | status = "okay"; |
| 318 | gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ |
| 319 | "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ |
| 320 | "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ |
| 321 | "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ |
| 322 | "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ |
| 323 | "I2C1_SDA", "", "", "", "", /* 25 - 29 */ |
| 324 | "", "", "", "", "", /* 30 - 34 */ |
| 325 | "", "", "", "", "", /* 35 - 39 */ |
| 326 | "", "", "", "", "", /* 40 - 44 */ |
| 327 | "", "", "", "", "", /* 45 - 49 */ |
| 328 | "", "", "", "", "", /* 50 - 54 */ |
| 329 | "", "", "", "", "", /* 55 - 59 */ |
| 330 | "", "", "", "", "", /* 60 - 64 */ |
| 331 | "", "", "", "", "", /* 65 - 69 */ |
| 332 | "", "", "", "", "", /* 70 - 74 */ |
| 333 | "", "", "", /* 75 - 77, MIO end and EMIO start */ |
| 334 | "", "", /* 78 - 79 */ |
| 335 | "", "", "", "", "", /* 80 - 84 */ |
| 336 | "", "", "", "", "", /* 85 - 89 */ |
| 337 | "", "", "", "", "", /* 90 - 94 */ |
| 338 | "", "", "", "", "", /* 95 - 99 */ |
| 339 | "", "", "", "", "", /* 100 - 104 */ |
| 340 | "", "", "", "", "", /* 105 - 109 */ |
| 341 | "", "", "", "", "", /* 110 - 114 */ |
| 342 | "", "", "", "", "", /* 115 - 119 */ |
| 343 | "", "", "", "", "", /* 120 - 124 */ |
| 344 | "", "", "", "", "", /* 125 - 129 */ |
| 345 | "", "", "", "", "", /* 130 - 134 */ |
| 346 | "", "", "", "", "", /* 135 - 139 */ |
| 347 | "", "", "", "", "", /* 140 - 144 */ |
| 348 | "", "", "", "", "", /* 145 - 149 */ |
| 349 | "", "", "", "", "", /* 150 - 154 */ |
| 350 | "", "", "", "", "", /* 155 - 159 */ |
| 351 | "", "", "", "", "", /* 160 - 164 */ |
| 352 | "", "", "", "", "", /* 165 - 169 */ |
| 353 | "", "", "", ""; /* 170 - 173 */ |
| 354 | }; |
| 355 | |
| 356 | &xilinx_ams { |
| 357 | status = "okay"; |
| 358 | }; |
| 359 | |
| 360 | &ams_ps { |
| 361 | status = "okay"; |
| 362 | }; |
| 363 | |
| 364 | &ams_pl { |
| 365 | status = "okay"; |
| 366 | }; |
| 367 | |
| 368 | &zynqmp_dpsub { |
| 369 | status = "okay"; |
| 370 | }; |
| 371 | |
| 372 | &rtc { |
| 373 | status = "okay"; |
| 374 | }; |
| 375 | |
| 376 | &lpd_dma_chan1 { |
| 377 | status = "okay"; |
| 378 | }; |
| 379 | |
| 380 | &lpd_dma_chan2 { |
| 381 | status = "okay"; |
| 382 | }; |
| 383 | |
| 384 | &lpd_dma_chan3 { |
| 385 | status = "okay"; |
| 386 | }; |
| 387 | |
| 388 | &lpd_dma_chan4 { |
| 389 | status = "okay"; |
| 390 | }; |
| 391 | |
| 392 | &lpd_dma_chan5 { |
| 393 | status = "okay"; |
| 394 | }; |
| 395 | |
| 396 | &lpd_dma_chan6 { |
| 397 | status = "okay"; |
| 398 | }; |
| 399 | |
| 400 | &lpd_dma_chan7 { |
| 401 | status = "okay"; |
| 402 | }; |
| 403 | |
| 404 | &lpd_dma_chan8 { |
| 405 | status = "okay"; |
| 406 | }; |
| 407 | |
| 408 | &fpd_dma_chan1 { |
| 409 | status = "okay"; |
| 410 | }; |
| 411 | |
| 412 | &fpd_dma_chan2 { |
| 413 | status = "okay"; |
| 414 | }; |
| 415 | |
| 416 | &fpd_dma_chan3 { |
| 417 | status = "okay"; |
| 418 | }; |
| 419 | |
| 420 | &fpd_dma_chan4 { |
| 421 | status = "okay"; |
| 422 | }; |
| 423 | |
| 424 | &fpd_dma_chan5 { |
| 425 | status = "okay"; |
| 426 | }; |
| 427 | |
| 428 | &fpd_dma_chan6 { |
| 429 | status = "okay"; |
| 430 | }; |
| 431 | |
| 432 | &fpd_dma_chan7 { |
| 433 | status = "okay"; |
| 434 | }; |
| 435 | |
| 436 | &fpd_dma_chan8 { |
| 437 | status = "okay"; |
| 438 | }; |
| 439 | |
| 440 | &gpu { |
| 441 | status = "okay"; |
| 442 | }; |
| 443 | |
| 444 | &lpd_watchdog { |
| 445 | status = "okay"; |
| 446 | }; |
| 447 | |
| 448 | &watchdog0 { |
| 449 | status = "okay"; |
| 450 | }; |
| 451 | |
| 452 | &cpu_opp_table { |
| 453 | opp00 { |
| 454 | opp-hz = /bits/ 64 <1333333333>; |
| 455 | }; |
| 456 | opp01 { |
| 457 | opp-hz = /bits/ 64 <666666666>; |
| 458 | }; |
| 459 | opp02 { |
| 460 | opp-hz = /bits/ 64 <444444444>; |
| 461 | }; |
| 462 | opp03 { |
| 463 | opp-hz = /bits/ 64 <333333333>; |
| 464 | }; |
| 465 | }; |