blob: 8360bb851ac03f4a2f55e727ba7b2ec39a9e9828 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2017~2018 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8qxp.dtsi"
9#include <dt-bindings/usb/pd.h>
10
11/ {
12 model = "Freescale i.MX8QXP MEK";
13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
14
15 chosen {
16 stdout-path = &lpuart0;
17 };
18
19 memory@80000000 {
20 device_type = "memory";
21 reg = <0x00000000 0x80000000 0 0x40000000>;
22 };
23
24 reg_usdhc2_vmmc: usdhc2-vmmc {
25 compatible = "regulator-fixed";
26 regulator-name = "SD1_SPWR";
27 regulator-min-microvolt = <3000000>;
28 regulator-max-microvolt = <3000000>;
29 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
30 enable-active-high;
31 };
32
33 gpio-sbu-mux {
Tom Rini93743d22024-04-01 09:08:13 -040034 compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
Tom Rini53633a82024-02-29 12:33:36 -050035 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_typec_mux>;
37 select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>;
38 enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
39 orientation-switch;
40
41 port {
42 usb3_data_ss: endpoint {
43 remote-endpoint = <&typec_con_ss>;
44 };
45 };
46 };
47};
48
49&dsp {
50 status = "okay";
51};
52
Tom Rini93743d22024-04-01 09:08:13 -040053&dsp_reserved {
54 status = "okay";
55};
56
Tom Rini53633a82024-02-29 12:33:36 -050057&fec1 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_fec1>;
60 phy-mode = "rgmii-id";
61 phy-handle = <&ethphy0>;
62 fsl,magic-packet;
63 status = "okay";
64
65 mdio {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 ethphy0: ethernet-phy@0 {
70 compatible = "ethernet-phy-ieee802.3-c22";
71 reg = <0>;
72 };
73 };
74};
75
76&i2c1 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 clock-frequency = <100000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
82 status = "okay";
83
84 i2c-mux@71 {
85 compatible = "nxp,pca9646", "nxp,pca9546";
86 #address-cells = <1>;
87 #size-cells = <0>;
88 reg = <0x71>;
89 reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>;
90
91 i2c@0 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 reg = <0>;
95
96 max7322: gpio@68 {
97 compatible = "maxim,max7322";
98 reg = <0x68>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 };
102 };
103
104 i2c@1 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 reg = <1>;
108 };
109
110 i2c@2 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 reg = <2>;
114
115 pressure-sensor@60 {
116 compatible = "fsl,mpl3115";
117 reg = <0x60>;
118 };
119 };
120
121 i2c@3 {
122 #address-cells = <1>;
123 #size-cells = <0>;
124 reg = <3>;
125
126 pca9557_a: gpio@1a {
127 compatible = "nxp,pca9557";
128 reg = <0x1a>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 };
132
133 pca9557_b: gpio@1d {
134 compatible = "nxp,pca9557";
135 reg = <0x1d>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 };
139
140 light-sensor@44 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_isl29023>;
143 compatible = "isil,isl29023";
144 reg = <0x44>;
145 interrupt-parent = <&lsio_gpio1>;
146 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
147 };
148 };
149 };
150
151 ptn5110: tcpc@50 {
152 compatible = "nxp,ptn5110";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_typec>;
155 reg = <0x50>;
156 interrupt-parent = <&lsio_gpio1>;
157 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
158
Tom Rini53633a82024-02-29 12:33:36 -0500159 usb_con1: connector {
160 compatible = "usb-c-connector";
161 label = "USB-C";
162 power-role = "source";
163 data-role = "dual";
164 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
165
166 ports {
167 #address-cells = <1>;
168 #size-cells = <0>;
169
Tom Rini93743d22024-04-01 09:08:13 -0400170 port@0 {
171 reg = <0>;
172
173 typec_dr_sw: endpoint {
174 remote-endpoint = <&usb3_drd_sw>;
175 };
176 };
177
Tom Rini53633a82024-02-29 12:33:36 -0500178 port@1 {
179 reg = <1>;
Tom Rini93743d22024-04-01 09:08:13 -0400180
Tom Rini53633a82024-02-29 12:33:36 -0500181 typec_con_ss: endpoint {
182 remote-endpoint = <&usb3_data_ss>;
183 };
184 };
185 };
186 };
187 };
188
189};
190
191&lpuart0 {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_lpuart0>;
194 status = "okay";
195};
196
197&lpuart2 {
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_lpuart2>;
200 status = "okay";
201};
202
203&lpuart3 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_lpuart3>;
206 status = "okay";
207};
208
209&mu_m0 {
210 status = "okay";
211};
212
213&mu1_m0 {
214 status = "okay";
215};
216
217&scu_key {
218 status = "okay";
219};
220
221&thermal_zones {
222 pmic-thermal {
223 polling-delay-passive = <250>;
224 polling-delay = <2000>;
225 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
226
227 trips {
228 pmic_alert0: trip0 {
229 temperature = <110000>;
230 hysteresis = <2000>;
231 type = "passive";
232 };
233
234 pmic_crit0: trip1 {
235 temperature = <125000>;
236 hysteresis = <2000>;
237 type = "critical";
238 };
239 };
240
241 cooling-maps {
242 map0 {
243 trip = <&pmic_alert0>;
244 cooling-device =
245 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
246 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
247 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
248 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
249 };
250 };
251 };
252};
253
254&usdhc1 {
255 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
256 assigned-clock-rates = <200000000>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_usdhc1>;
259 bus-width = <8>;
260 no-sd;
261 no-sdio;
262 non-removable;
263 status = "okay";
264};
265
266&usdhc2 {
267 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
268 assigned-clock-rates = <200000000>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_usdhc2>;
271 bus-width = <4>;
272 vmmc-supply = <&reg_usdhc2_vmmc>;
273 cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
274 wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
275 status = "okay";
276};
277
278&usb3_phy {
279 status = "okay";
280};
281
282&usbotg3 {
283 status = "okay";
284};
285
286&usbotg3_cdns3 {
287 dr_mode = "otg";
288 usb-role-switch;
289 status = "okay";
290
291 port {
292 usb3_drd_sw: endpoint {
293 remote-endpoint = <&typec_dr_sw>;
294 };
295 };
296};
297
298
299&vpu {
300 compatible = "nxp,imx8qxp-vpu";
301 status = "okay";
302};
303
304&vpu_core0 {
305 reg = <0x2d040000 0x10000>;
306 memory-region = <&decoder_boot>, <&decoder_rpc>;
307 status = "okay";
308};
309
310&vpu_core1 {
311 reg = <0x2d050000 0x10000>;
312 memory-region = <&encoder_boot>, <&encoder_rpc>;
313 status = "okay";
314};
315
316&iomuxc {
317 pinctrl_fec1: fec1grp {
318 fsl,pins = <
319 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
320 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
321 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
322 IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
323 IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
324 IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
325 IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
326 IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
327 IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
328 IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
329 IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
330 IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
331 IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
332 IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
333 >;
334 };
335
336 pinctrl_ioexp_rst: ioexprstgrp {
337 fsl,pins = <
338 IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
339 >;
340 };
341
342 pinctrl_isl29023: isl29023grp {
343 fsl,pins = <
344 IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021
345 >;
346 };
347
348 pinctrl_lpi2c1: lpi2c1grp {
349 fsl,pins = <
350 IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
351 IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
352 >;
353 };
354
355 pinctrl_lpuart0: lpuart0grp {
356 fsl,pins = <
357 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
358 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
359 >;
360 };
361
362 pinctrl_lpuart2: lpuart2grp {
363 fsl,pins = <
364 IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020
365 IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020
366 >;
367 };
368
369 pinctrl_lpuart3: lpuart3grp {
370 fsl,pins = <
371 IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
372 IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
373 >;
374 };
375
376 pinctrl_typec: typecgrp {
377 fsl,pins = <
378 IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
379 >;
380 };
381
382 pinctrl_typec_mux: typecmuxgrp {
383 fsl,pins = <
384 IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
385 >;
386 };
387
388 pinctrl_usdhc1: usdhc1grp {
389 fsl,pins = <
390 IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
391 IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
392 IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
393 IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
394 IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
395 IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
396 IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
397 IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
398 IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
399 IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
400 IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
401 >;
402 };
403
404 pinctrl_usdhc2: usdhc2grp {
405 fsl,pins = <
406 IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
407 IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
408 IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
409 IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
410 IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
411 IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
412 IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
413 >;
414 };
415};