Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm64 / freescale / imx8mn-var-som.dtsi
blob: b364307868f25eb05507c651afa6fee8d0c8423f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
6 */
7
8#include "imx8mn.dtsi"
9
10/ {
11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
13
14 chosen {
15 stdout-path = &uart4;
16 };
17
18 memory@40000000 {
19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0x40000000>;
21 };
22
23 reg_eth_phy: regulator-eth-phy {
24 compatible = "regulator-fixed";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
27 regulator-name = "eth_phy_pwr";
28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>;
30 regulator-enable-ramp-delay = <20000>;
31 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
32 enable-active-high;
33 };
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]34
35 reg_3v3_fixed: regulator-3v3-fixed {
36 compatible = "regulator-fixed";
37 regulator-name = "fixed_3v3";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 };
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]42};
43
44&A53_0 {
45 cpu-supply = <&buck2_reg>;
46};
47
48&A53_1 {
49 cpu-supply = <&buck2_reg>;
50};
51
52&A53_2 {
53 cpu-supply = <&buck2_reg>;
54};
55
56&A53_3 {
57 cpu-supply = <&buck2_reg>;
58};
59
60&ecspi1 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_ecspi1>;
63 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
64 <&gpio1 0 GPIO_ACTIVE_LOW>;
65 /delete-property/ dmas;
66 /delete-property/ dma-names;
67 status = "okay";
68
69 /* Resistive touch controller */
70 touchscreen@0 {
71 reg = <0>;
72 compatible = "ti,ads7846";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_restouch>;
75 interrupt-parent = <&gpio1>;
76 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
77
78 spi-max-frequency = <1500000>;
79 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
80
81 ti,x-min = /bits/ 16 <125>;
82 touchscreen-size-x = <4008>;
83 ti,y-min = /bits/ 16 <282>;
84 touchscreen-size-y = <3864>;
85 ti,x-plate-ohms = /bits/ 16 <180>;
86 touchscreen-max-pressure = <255>;
87 touchscreen-average-samples = <10>;
88 ti,debounce-tol = /bits/ 16 <3>;
89 ti,debounce-rep = /bits/ 16 <1>;
90 ti,settle-delay-usec = /bits/ 16 <150>;
91 ti,keep-vref-on;
92 wakeup-source;
93 };
94};
95
96&fec1 {
97 pinctrl-names = "default", "sleep";
98 pinctrl-0 = <&pinctrl_fec1>;
99 pinctrl-1 = <&pinctrl_fec1_sleep>;
100 phy-mode = "rgmii";
101 phy-handle = <&ethphy>;
102 phy-supply = <&reg_eth_phy>;
103 fsl,magic-packet;
104 status = "okay";
105
106 mdio {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
111 compatible = "ethernet-phy-ieee802.3-c22";
112 reg = <4>;
113 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
114 reset-assert-us = <10000>;
115 /*
116 * Deassert delay:
117 * ADIN1300 requires 5ms.
118 * AR8033 requires 1ms.
119 */
120 reset-deassert-us = <20000>;
121 };
122 };
123};
124
125&i2c1 {
126 clock-frequency = <400000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay";
130
131 pmic@4b {
132 compatible = "rohm,bd71847";
133 reg = <0x4b>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_pmic>;
136 interrupt-parent = <&gpio2>;
137 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
138 rohm,reset-snvs-powered;
139
140 regulators {
141 buck1_reg: BUCK1 {
142 regulator-name = "buck1";
143 regulator-min-microvolt = <700000>;
144 regulator-max-microvolt = <1300000>;
145 regulator-boot-on;
146 regulator-always-on;
147 regulator-ramp-delay = <1250>;
148 };
149
150 buck2_reg: BUCK2 {
151 regulator-name = "buck2";
152 regulator-min-microvolt = <700000>;
153 regulator-max-microvolt = <1300000>;
154 regulator-boot-on;
155 regulator-always-on;
156 regulator-ramp-delay = <1250>;
157 rohm,dvs-run-voltage = <1000000>;
158 rohm,dvs-idle-voltage = <900000>;
159 };
160
161 buck3_reg: BUCK3 {
162 regulator-name = "buck3";
163 regulator-min-microvolt = <700000>;
164 regulator-max-microvolt = <1350000>;
165 regulator-boot-on;
166 regulator-always-on;
167 };
168
169 buck4_reg: BUCK4 {
170 regulator-name = "buck4";
171 regulator-min-microvolt = <2600000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 buck5_reg: BUCK5 {
178 regulator-name = "buck5";
179 regulator-min-microvolt = <1605000>;
180 regulator-max-microvolt = <1995000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184
185 buck6_reg: BUCK6 {
186 regulator-name = "buck6";
187 regulator-min-microvolt = <800000>;
188 regulator-max-microvolt = <1400000>;
189 regulator-boot-on;
190 regulator-always-on;
191 };
192
193 ldo1_reg: LDO1 {
194 regulator-name = "ldo1";
195 regulator-min-microvolt = <1600000>;
196 regulator-max-microvolt = <1900000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 ldo2_reg: LDO2 {
202 regulator-name = "ldo2";
203 regulator-min-microvolt = <800000>;
204 regulator-max-microvolt = <900000>;
205 regulator-boot-on;
206 regulator-always-on;
207 };
208
209 ldo3_reg: LDO3 {
210 regulator-name = "ldo3";
211 regulator-min-microvolt = <1800000>;
212 regulator-max-microvolt = <3300000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 ldo4_reg: LDO4 {
218 regulator-name = "ldo4";
219 regulator-min-microvolt = <900000>;
220 regulator-max-microvolt = <1800000>;
221 regulator-always-on;
222 };
223
224 ldo5_reg: LDO5 {
225 regulator-name = "ldo5";
226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <1800000>;
228 regulator-always-on;
229 };
230
231 ldo6_reg: LDO6 {
232 regulator-name = "ldo6";
233 regulator-min-microvolt = <900000>;
234 regulator-max-microvolt = <1800000>;
235 regulator-boot-on;
236 regulator-always-on;
237 };
238 };
239 };
240
241 eeprom_som: eeprom@52 {
242 compatible = "atmel,24c04";
243 reg = <0x52>;
244 pagesize = <16>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]245 vcc-supply = <&reg_3v3_fixed>;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]246 };
247};
248
249&i2c3 {
250 clock-frequency = <400000>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>;
253 status = "okay";
254
255 /* TODO: configure audio, as of now just put a placeholder */
256 wm8904: codec@1a {
257 compatible = "wlf,wm8904";
258 reg = <0x1a>;
259 status = "disabled";
260 };
261};
262
263&snvs_pwrkey {
264 status = "okay";
265};
266
267/* Bluetooth */
268&uart2 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart2>;
271 assigned-clocks = <&clk IMX8MN_CLK_UART2>;
272 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
273 uart-has-rtscts;
274 status = "okay";
275};
276
277/* Console */
278&uart4 {
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart4>;
281 status = "okay";
282};
283
284&usbotg1 {
285 dr_mode = "otg";
286 usb-role-switch;
287 status = "okay";
288};
289
290/* WIFI */
291&usdhc1 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 pinctrl-names = "default", "state_100mhz", "state_200mhz";
295 pinctrl-0 = <&pinctrl_usdhc1>;
296 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
297 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
298 bus-width = <4>;
299 non-removable;
300 keep-power-in-suspend;
301 status = "okay";
302
303 brcmf: bcrmf@1 {
304 reg = <1>;
305 compatible = "brcm,bcm4329-fmac";
306 };
307};
308
309/* SD */
310&usdhc2 {
311 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
312 assigned-clock-rates = <200000000>;
313 pinctrl-names = "default", "state_100mhz", "state_200mhz";
314 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
315 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
316 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
317 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
318 bus-width = <4>;
319 vmmc-supply = <&reg_usdhc2_vmmc>;
320 status = "okay";
321};
322
323/* eMMC */
324&usdhc3 {
325 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
326 assigned-clock-rates = <400000000>;
327 pinctrl-names = "default", "state_100mhz", "state_200mhz";
328 pinctrl-0 = <&pinctrl_usdhc3>;
329 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
330 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
331 bus-width = <8>;
332 non-removable;
333 status = "okay";
334};
335
336&wdog1 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_wdog>;
339 fsl,ext-reset-output;
340 status = "okay";
341};
342
343&iomuxc {
344 pinctrl_ecspi1: ecspi1grp {
345 fsl,pins = <
346 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
347 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
348 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
349 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
350 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
351 >;
352 };
353
354 pinctrl_fec1: fec1grp {
355 fsl,pins = <
356 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
357 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
358 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
359 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
360 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
361 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
362 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
363 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
364 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
365 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
366 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
367 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
368 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
369 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
370 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159
371 >;
372 };
373
374 pinctrl_fec1_sleep: fec1sleepgrp {
375 fsl,pins = <
376 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
377 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
378 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
379 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
380 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
381 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
382 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
383 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
384 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
385 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
386 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
387 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
388 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
389 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
390 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
391 >;
392 };
393
394 pinctrl_i2c1: i2c1grp {
395 fsl,pins = <
396 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
397 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
398 >;
399 };
400
401 pinctrl_i2c3: i2c3grp {
402 fsl,pins = <
403 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
404 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
405 >;
406 };
407
408 pinctrl_pmic: pmicirqgrp {
409 fsl,pins = <
410 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
411 >;
412 };
413
414 pinctrl_reg_eth_phy: regethphygrp {
415 fsl,pins = <
416 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
417 >;
418 };
419
420 pinctrl_restouch: restouchgrp {
421 fsl,pins = <
422 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
423 >;
424 };
425
426 pinctrl_uart2: uart2grp {
427 fsl,pins = <
428 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
429 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
430 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
431 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
432 >;
433 };
434
435 pinctrl_uart4: uart4grp {
436 fsl,pins = <
437 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
438 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
439 >;
440 };
441
442 pinctrl_usdhc1: usdhc1grp {
443 fsl,pins = <
444 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
445 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
446 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
447 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
448 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
449 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
450 >;
451 };
452
453 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
454 fsl,pins = <
455 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
456 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
457 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
458 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
459 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
460 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
461 >;
462 };
463
464 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
465 fsl,pins = <
466 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
467 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
468 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
469 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
470 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
471 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
472 >;
473 };
474
475 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
476 fsl,pins = <
477 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
478 >;
479 };
480
481 pinctrl_usdhc2: usdhc2grp {
482 fsl,pins = <
483 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
484 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
485 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
486 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
487 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
488 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
489 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
490 >;
491 };
492
493 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
494 fsl,pins = <
495 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
496 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
497 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
498 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
499 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
500 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
501 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
502 >;
503 };
504
505 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
506 fsl,pins = <
507 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
508 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
509 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
510 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
511 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
512 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
513 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
514 >;
515 };
516
517 pinctrl_usdhc3: usdhc3grp {
518 fsl,pins = <
519 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
520 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
521 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
522 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
523 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
524 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
525 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
526 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
527 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
528 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
529 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
530 >;
531 };
532
533 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
534 fsl,pins = <
535 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
536 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
537 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
538 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
539 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
540 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
541 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
542 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
543 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
544 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
545 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
546 >;
547 };
548
549 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
550 fsl,pins = <
551 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
552 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
553 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
554 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
555 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
556 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
557 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
558 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
559 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
560 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
561 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
562 >;
563 };
564
565 pinctrl_wdog: wdoggrp {
566 fsl,pins = <
567 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
568 >;
569 };
570};