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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm64 / amlogic / meson-axg.dtsi
blob: 7e5ac9db93f8a7dae069fc91515b3f26d0f74b9d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15#include <dt-bindings/power/meson-axg-power.h>
16
17/ {
18 compatible = "amlogic,meson-axg";
19
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23
24 tdmif_a: audio-controller-0 {
25 compatible = "amlogic,axg-tdm-iface";
26 #sound-dai-cells = <0>;
27 sound-name-prefix = "TDM_A";
28 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31 clock-names = "mclk", "sclk", "lrclk";
32 status = "disabled";
33 };
34
35 tdmif_b: audio-controller-1 {
36 compatible = "amlogic,axg-tdm-iface";
37 #sound-dai-cells = <0>;
38 sound-name-prefix = "TDM_B";
39 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42 clock-names = "mclk", "sclk", "lrclk";
43 status = "disabled";
44 };
45
46 tdmif_c: audio-controller-2 {
47 compatible = "amlogic,axg-tdm-iface";
48 #sound-dai-cells = <0>;
49 sound-name-prefix = "TDM_C";
50 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53 clock-names = "mclk", "sclk", "lrclk";
54 status = "disabled";
55 };
56
57 arm-pmu {
58 compatible = "arm,cortex-a53-pmu";
59 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64 };
65
66 cpus {
67 #address-cells = <0x2>;
68 #size-cells = <0x0>;
69
70 cpu0: cpu@0 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a53";
73 reg = <0x0 0x0>;
74 enable-method = "psci";
75 next-level-cache = <&l2>;
76 clocks = <&scpi_dvfs 0>;
77 };
78
79 cpu1: cpu@1 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a53";
82 reg = <0x0 0x1>;
83 enable-method = "psci";
84 next-level-cache = <&l2>;
85 clocks = <&scpi_dvfs 0>;
86 };
87
88 cpu2: cpu@2 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a53";
91 reg = <0x0 0x2>;
92 enable-method = "psci";
93 next-level-cache = <&l2>;
94 clocks = <&scpi_dvfs 0>;
95 };
96
97 cpu3: cpu@3 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a53";
100 reg = <0x0 0x3>;
101 enable-method = "psci";
102 next-level-cache = <&l2>;
103 clocks = <&scpi_dvfs 0>;
104 };
105
106 l2: l2-cache0 {
107 compatible = "cache";
108 cache-level = <2>;
109 cache-unified;
110 };
111 };
112
113 sm: secure-monitor {
114 compatible = "amlogic,meson-gxbb-sm";
115 };
116
117 efuse: efuse {
118 compatible = "amlogic,meson-gxbb-efuse";
119 clocks = <&clkc CLKID_EFUSE>;
120 #address-cells = <1>;
121 #size-cells = <1>;
122 read-only;
123 secure-monitor = <&sm>;
124 };
125
126 psci {
127 compatible = "arm,psci-1.0";
128 method = "smc";
129 };
130
131 reserved-memory {
132 #address-cells = <2>;
133 #size-cells = <2>;
134 ranges;
135
136 /* 16 MiB reserved for Hardware ROM Firmware */
137 hwrom_reserved: hwrom@0 {
138 reg = <0x0 0x0 0x0 0x1000000>;
139 no-map;
140 };
141
142 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
143 secmon_reserved: secmon@5000000 {
144 reg = <0x0 0x05000000 0x0 0x300000>;
145 no-map;
146 };
147 };
148
149 scpi {
150 compatible = "arm,scpi-pre-1.0";
151 mboxes = <&mailbox 1 &mailbox 2>;
152 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
153
154 scpi_clocks: clocks {
155 compatible = "arm,scpi-clocks";
156
157 scpi_dvfs: clocks-0 {
158 compatible = "arm,scpi-dvfs-clocks";
159 #clock-cells = <1>;
160 clock-indices = <0>;
161 clock-output-names = "vcpu";
162 };
163 };
164
165 scpi_sensors: sensors {
166 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
167 #thermal-sensor-cells = <1>;
168 };
169 };
170
171 soc {
172 compatible = "simple-bus";
173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges;
176
177 pcieA: pcie@f9800000 {
178 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
179 reg = <0x0 0xf9800000 0x0 0x400000>,
180 <0x0 0xff646000 0x0 0x2000>,
181 <0x0 0xf9f00000 0x0 0x100000>;
182 reg-names = "elbi", "cfg", "config";
183 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
184 #interrupt-cells = <1>;
185 interrupt-map-mask = <0 0 0 0>;
186 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
187 bus-range = <0x0 0xff>;
188 #address-cells = <3>;
189 #size-cells = <2>;
190 device_type = "pci";
191 ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
192
193 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
194 clock-names = "general", "pclk", "port";
195 resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
196 reset-names = "port", "apb";
197 num-lanes = <1>;
198 phys = <&pcie_phy>;
199 phy-names = "pcie";
200 status = "disabled";
201 };
202
203 pcieB: pcie@fa000000 {
204 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
205 reg = <0x0 0xfa000000 0x0 0x400000>,
206 <0x0 0xff648000 0x0 0x2000>,
207 <0x0 0xfa400000 0x0 0x100000>;
208 reg-names = "elbi", "cfg", "config";
209 interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
210 #interrupt-cells = <1>;
211 interrupt-map-mask = <0 0 0 0>;
212 interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
213 bus-range = <0x0 0xff>;
214 #address-cells = <3>;
215 #size-cells = <2>;
216 device_type = "pci";
217 ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
218
219 clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
220 clock-names = "general", "pclk", "port";
221 resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
222 reset-names = "port", "apb";
223 num-lanes = <1>;
224 phys = <&pcie_phy>;
225 phy-names = "pcie";
226 status = "disabled";
227 };
228
229 usb: usb@ffe09080 {
230 compatible = "amlogic,meson-axg-usb-ctrl";
231 reg = <0x0 0xffe09080 0x0 0x20>;
232 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
233 #address-cells = <2>;
234 #size-cells = <2>;
235 ranges;
236
237 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
238 clock-names = "usb_ctrl", "ddr";
239 resets = <&reset RESET_USB_OTG>;
240
241 dr_mode = "otg";
242
243 phys = <&usb2_phy1>;
244 phy-names = "usb2-phy1";
245
246 dwc2: usb@ff400000 {
247 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
248 reg = <0x0 0xff400000 0x0 0x40000>;
249 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&clkc CLKID_USB1>;
251 clock-names = "otg";
252 phys = <&usb2_phy1>;
253 dr_mode = "peripheral";
254 g-rx-fifo-size = <192>;
255 g-np-tx-fifo-size = <128>;
256 g-tx-fifo-size = <128 128 16 16 16>;
257 };
258
259 dwc3: usb@ff500000 {
260 compatible = "snps,dwc3";
261 reg = <0x0 0xff500000 0x0 0x100000>;
262 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
263 dr_mode = "host";
264 maximum-speed = "high-speed";
265 snps,dis_u2_susphy_quirk;
266 };
267 };
268
269 ethmac: ethernet@ff3f0000 {
270 compatible = "amlogic,meson-axg-dwmac",
271 "snps,dwmac-3.70a",
272 "snps,dwmac";
273 reg = <0x0 0xff3f0000 0x0 0x10000>,
274 <0x0 0xff634540 0x0 0x8>;
275 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "macirq";
277 clocks = <&clkc CLKID_ETH>,
278 <&clkc CLKID_FCLK_DIV2>,
279 <&clkc CLKID_MPLL2>,
280 <&clkc CLKID_FCLK_DIV2>;
281 clock-names = "stmmaceth", "clkin0", "clkin1",
282 "timing-adjustment";
283 rx-fifo-depth = <4096>;
284 tx-fifo-depth = <2048>;
285 power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
286 status = "disabled";
287 };
288
289 pcie_phy: phy@ff644000 {
290 compatible = "amlogic,axg-pcie-phy";
291 reg = <0x0 0xff644000 0x0 0x1c>;
292 resets = <&reset RESET_PCIE_PHY>;
293 phys = <&mipi_pcie_analog_dphy>;
294 phy-names = "analog";
295 #phy-cells = <0>;
296 };
297
298 pdm: audio-controller@ff632000 {
299 compatible = "amlogic,axg-pdm";
300 reg = <0x0 0xff632000 0x0 0x34>;
301 #sound-dai-cells = <0>;
302 sound-name-prefix = "PDM";
303 clocks = <&clkc_audio AUD_CLKID_PDM>,
304 <&clkc_audio AUD_CLKID_PDM_DCLK>,
305 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
306 clock-names = "pclk", "dclk", "sysclk";
307 status = "disabled";
308 };
309
310 periphs: bus@ff634000 {
311 compatible = "simple-bus";
312 reg = <0x0 0xff634000 0x0 0x2000>;
313 #address-cells = <2>;
314 #size-cells = <2>;
315 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
316
317 hwrng: rng@18 {
318 compatible = "amlogic,meson-rng";
319 reg = <0x0 0x18 0x0 0x4>;
320 clocks = <&clkc CLKID_RNG0>;
321 clock-names = "core";
322 };
323
324 pinctrl_periphs: pinctrl@480 {
325 compatible = "amlogic,meson-axg-periphs-pinctrl";
326 #address-cells = <2>;
327 #size-cells = <2>;
328 ranges;
329
330 gpio: bank@480 {
331 reg = <0x0 0x00480 0x0 0x40>,
332 <0x0 0x004e8 0x0 0x14>,
333 <0x0 0x00520 0x0 0x14>,
334 <0x0 0x00430 0x0 0x3c>;
335 reg-names = "mux", "pull", "pull-enable", "gpio";
336 gpio-controller;
337 #gpio-cells = <2>;
338 gpio-ranges = <&pinctrl_periphs 0 0 86>;
339 };
340
341 i2c0_pins: i2c0 {
342 mux {
343 groups = "i2c0_sck",
344 "i2c0_sda";
345 function = "i2c0";
346 bias-disable;
347 };
348 };
349
350 i2c1_x_pins: i2c1_x {
351 mux {
352 groups = "i2c1_sck_x",
353 "i2c1_sda_x";
354 function = "i2c1";
355 bias-disable;
356 };
357 };
358
359 i2c1_z_pins: i2c1_z {
360 mux {
361 groups = "i2c1_sck_z",
362 "i2c1_sda_z";
363 function = "i2c1";
364 bias-disable;
365 };
366 };
367
368 i2c2_a_pins: i2c2_a {
369 mux {
370 groups = "i2c2_sck_a",
371 "i2c2_sda_a";
372 function = "i2c2";
373 bias-disable;
374 };
375 };
376
377 i2c2_x_pins: i2c2_x {
378 mux {
379 groups = "i2c2_sck_x",
380 "i2c2_sda_x";
381 function = "i2c2";
382 bias-disable;
383 };
384 };
385
386 i2c3_a6_pins: i2c3_a6 {
387 mux {
388 groups = "i2c3_sda_a6",
389 "i2c3_sck_a7";
390 function = "i2c3";
391 bias-disable;
392 };
393 };
394
395 i2c3_a12_pins: i2c3_a12 {
396 mux {
397 groups = "i2c3_sda_a12",
398 "i2c3_sck_a13";
399 function = "i2c3";
400 bias-disable;
401 };
402 };
403
404 i2c3_a19_pins: i2c3_a19 {
405 mux {
406 groups = "i2c3_sda_a19",
407 "i2c3_sck_a20";
408 function = "i2c3";
409 bias-disable;
410 };
411 };
412
413 emmc_pins: emmc {
414 mux-0 {
415 groups = "emmc_nand_d0",
416 "emmc_nand_d1",
417 "emmc_nand_d2",
418 "emmc_nand_d3",
419 "emmc_nand_d4",
420 "emmc_nand_d5",
421 "emmc_nand_d6",
422 "emmc_nand_d7",
423 "emmc_cmd";
424 function = "emmc";
425 bias-pull-up;
426 };
427
428 mux-1 {
429 groups = "emmc_clk";
430 function = "emmc";
431 bias-disable;
432 };
433 };
434
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]435 nand_all_pins: nand-all-pins {
436 mux {
437 groups = "emmc_nand_d0",
438 "emmc_nand_d1",
439 "emmc_nand_d2",
440 "emmc_nand_d3",
441 "emmc_nand_d4",
442 "emmc_nand_d5",
443 "emmc_nand_d6",
444 "emmc_nand_d7",
445 "nand_ce0",
446 "nand_ale",
447 "nand_cle",
448 "nand_wen_clk",
449 "nand_ren_wr";
450 function = "nand";
451 input-enable;
452 bias-pull-up;
453 };
454 };
455
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]456 emmc_ds_pins: emmc_ds {
457 mux {
458 groups = "emmc_ds";
459 function = "emmc";
460 bias-pull-down;
461 };
462 };
463
464 emmc_clk_gate_pins: emmc_clk_gate {
465 mux {
466 groups = "BOOT_8";
467 function = "gpio_periphs";
468 bias-pull-down;
469 };
470 };
471
472 eth_rgmii_x_pins: eth-x-rgmii {
473 mux {
474 groups = "eth_mdio_x",
475 "eth_mdc_x",
476 "eth_rgmii_rx_clk_x",
477 "eth_rx_dv_x",
478 "eth_rxd0_x",
479 "eth_rxd1_x",
480 "eth_rxd2_rgmii",
481 "eth_rxd3_rgmii",
482 "eth_rgmii_tx_clk",
483 "eth_txen_x",
484 "eth_txd0_x",
485 "eth_txd1_x",
486 "eth_txd2_rgmii",
487 "eth_txd3_rgmii";
488 function = "eth";
489 bias-disable;
490 };
491 };
492
493 eth_rgmii_y_pins: eth-y-rgmii {
494 mux {
495 groups = "eth_mdio_y",
496 "eth_mdc_y",
497 "eth_rgmii_rx_clk_y",
498 "eth_rx_dv_y",
499 "eth_rxd0_y",
500 "eth_rxd1_y",
501 "eth_rxd2_rgmii",
502 "eth_rxd3_rgmii",
503 "eth_rgmii_tx_clk",
504 "eth_txen_y",
505 "eth_txd0_y",
506 "eth_txd1_y",
507 "eth_txd2_rgmii",
508 "eth_txd3_rgmii";
509 function = "eth";
510 bias-disable;
511 };
512 };
513
514 eth_rmii_x_pins: eth-x-rmii {
515 mux {
516 groups = "eth_mdio_x",
517 "eth_mdc_x",
518 "eth_rgmii_rx_clk_x",
519 "eth_rx_dv_x",
520 "eth_rxd0_x",
521 "eth_rxd1_x",
522 "eth_txen_x",
523 "eth_txd0_x",
524 "eth_txd1_x";
525 function = "eth";
526 bias-disable;
527 };
528 };
529
530 eth_rmii_y_pins: eth-y-rmii {
531 mux {
532 groups = "eth_mdio_y",
533 "eth_mdc_y",
534 "eth_rgmii_rx_clk_y",
535 "eth_rx_dv_y",
536 "eth_rxd0_y",
537 "eth_rxd1_y",
538 "eth_txen_y",
539 "eth_txd0_y",
540 "eth_txd1_y";
541 function = "eth";
542 bias-disable;
543 };
544 };
545
546 mclk_b_pins: mclk_b {
547 mux {
548 groups = "mclk_b";
549 function = "mclk_b";
550 bias-disable;
551 };
552 };
553
554 mclk_c_pins: mclk_c {
555 mux {
556 groups = "mclk_c";
557 function = "mclk_c";
558 bias-disable;
559 };
560 };
561
562 pdm_dclk_a14_pins: pdm_dclk_a14 {
563 mux {
564 groups = "pdm_dclk_a14";
565 function = "pdm";
566 bias-disable;
567 };
568 };
569
570 pdm_dclk_a19_pins: pdm_dclk_a19 {
571 mux {
572 groups = "pdm_dclk_a19";
573 function = "pdm";
574 bias-disable;
575 };
576 };
577
578 pdm_din0_pins: pdm_din0 {
579 mux {
580 groups = "pdm_din0";
581 function = "pdm";
582 bias-disable;
583 };
584 };
585
586 pdm_din1_pins: pdm_din1 {
587 mux {
588 groups = "pdm_din1";
589 function = "pdm";
590 bias-disable;
591 };
592 };
593
594 pdm_din2_pins: pdm_din2 {
595 mux {
596 groups = "pdm_din2";
597 function = "pdm";
598 bias-disable;
599 };
600 };
601
602 pdm_din3_pins: pdm_din3 {
603 mux {
604 groups = "pdm_din3";
605 function = "pdm";
606 bias-disable;
607 };
608 };
609
610 pwm_a_a_pins: pwm_a_a {
611 mux {
612 groups = "pwm_a_a";
613 function = "pwm_a";
614 bias-disable;
615 };
616 };
617
618 pwm_a_x18_pins: pwm_a_x18 {
619 mux {
620 groups = "pwm_a_x18";
621 function = "pwm_a";
622 bias-disable;
623 };
624 };
625
626 pwm_a_x20_pins: pwm_a_x20 {
627 mux {
628 groups = "pwm_a_x20";
629 function = "pwm_a";
630 bias-disable;
631 };
632 };
633
634 pwm_a_z_pins: pwm_a_z {
635 mux {
636 groups = "pwm_a_z";
637 function = "pwm_a";
638 bias-disable;
639 };
640 };
641
642 pwm_b_a_pins: pwm_b_a {
643 mux {
644 groups = "pwm_b_a";
645 function = "pwm_b";
646 bias-disable;
647 };
648 };
649
650 pwm_b_x_pins: pwm_b_x {
651 mux {
652 groups = "pwm_b_x";
653 function = "pwm_b";
654 bias-disable;
655 };
656 };
657
658 pwm_b_z_pins: pwm_b_z {
659 mux {
660 groups = "pwm_b_z";
661 function = "pwm_b";
662 bias-disable;
663 };
664 };
665
666 pwm_c_a_pins: pwm_c_a {
667 mux {
668 groups = "pwm_c_a";
669 function = "pwm_c";
670 bias-disable;
671 };
672 };
673
674 pwm_c_x10_pins: pwm_c_x10 {
675 mux {
676 groups = "pwm_c_x10";
677 function = "pwm_c";
678 bias-disable;
679 };
680 };
681
682 pwm_c_x17_pins: pwm_c_x17 {
683 mux {
684 groups = "pwm_c_x17";
685 function = "pwm_c";
686 bias-disable;
687 };
688 };
689
690 pwm_d_x11_pins: pwm_d_x11 {
691 mux {
692 groups = "pwm_d_x11";
693 function = "pwm_d";
694 bias-disable;
695 };
696 };
697
698 pwm_d_x16_pins: pwm_d_x16 {
699 mux {
700 groups = "pwm_d_x16";
701 function = "pwm_d";
702 bias-disable;
703 };
704 };
705
706 sdio_pins: sdio {
707 mux-0 {
708 groups = "sdio_d0",
709 "sdio_d1",
710 "sdio_d2",
711 "sdio_d3",
712 "sdio_cmd";
713 function = "sdio";
714 bias-pull-up;
715 };
716
717 mux-1 {
718 groups = "sdio_clk";
719 function = "sdio";
720 bias-disable;
721 };
722 };
723
724 sdio_clk_gate_pins: sdio_clk_gate {
725 mux {
726 groups = "GPIOX_4";
727 function = "gpio_periphs";
728 bias-pull-down;
729 };
730 };
731
732 spdif_in_z_pins: spdif_in_z {
733 mux {
734 groups = "spdif_in_z";
735 function = "spdif_in";
736 bias-disable;
737 };
738 };
739
740 spdif_in_a1_pins: spdif_in_a1 {
741 mux {
742 groups = "spdif_in_a1";
743 function = "spdif_in";
744 bias-disable;
745 };
746 };
747
748 spdif_in_a7_pins: spdif_in_a7 {
749 mux {
750 groups = "spdif_in_a7";
751 function = "spdif_in";
752 bias-disable;
753 };
754 };
755
756 spdif_in_a19_pins: spdif_in_a19 {
757 mux {
758 groups = "spdif_in_a19";
759 function = "spdif_in";
760 bias-disable;
761 };
762 };
763
764 spdif_in_a20_pins: spdif_in_a20 {
765 mux {
766 groups = "spdif_in_a20";
767 function = "spdif_in";
768 bias-disable;
769 };
770 };
771
772 spdif_out_a1_pins: spdif_out_a1 {
773 mux {
774 groups = "spdif_out_a1";
775 function = "spdif_out";
776 bias-disable;
777 };
778 };
779
780 spdif_out_a11_pins: spdif_out_a11 {
781 mux {
782 groups = "spdif_out_a11";
783 function = "spdif_out";
784 bias-disable;
785 };
786 };
787
788 spdif_out_a19_pins: spdif_out_a19 {
789 mux {
790 groups = "spdif_out_a19";
791 function = "spdif_out";
792 bias-disable;
793 };
794 };
795
796 spdif_out_a20_pins: spdif_out_a20 {
797 mux {
798 groups = "spdif_out_a20";
799 function = "spdif_out";
800 bias-disable;
801 };
802 };
803
804 spdif_out_z_pins: spdif_out_z {
805 mux {
806 groups = "spdif_out_z";
807 function = "spdif_out";
808 bias-disable;
809 };
810 };
811
812 spi0_pins: spi0 {
813 mux {
814 groups = "spi0_miso",
815 "spi0_mosi",
816 "spi0_clk";
817 function = "spi0";
818 bias-disable;
819 };
820 };
821
822 spi0_ss0_pins: spi0_ss0 {
823 mux {
824 groups = "spi0_ss0";
825 function = "spi0";
826 bias-disable;
827 };
828 };
829
830 spi0_ss1_pins: spi0_ss1 {
831 mux {
832 groups = "spi0_ss1";
833 function = "spi0";
834 bias-disable;
835 };
836 };
837
838 spi0_ss2_pins: spi0_ss2 {
839 mux {
840 groups = "spi0_ss2";
841 function = "spi0";
842 bias-disable;
843 };
844 };
845
846 spi1_a_pins: spi1_a {
847 mux {
848 groups = "spi1_miso_a",
849 "spi1_mosi_a",
850 "spi1_clk_a";
851 function = "spi1";
852 bias-disable;
853 };
854 };
855
856 spi1_ss0_a_pins: spi1_ss0_a {
857 mux {
858 groups = "spi1_ss0_a";
859 function = "spi1";
860 bias-disable;
861 };
862 };
863
864 spi1_ss1_pins: spi1_ss1 {
865 mux {
866 groups = "spi1_ss1";
867 function = "spi1";
868 bias-disable;
869 };
870 };
871
872 spi1_x_pins: spi1_x {
873 mux {
874 groups = "spi1_miso_x",
875 "spi1_mosi_x",
876 "spi1_clk_x";
877 function = "spi1";
878 bias-disable;
879 };
880 };
881
882 spi1_ss0_x_pins: spi1_ss0_x {
883 mux {
884 groups = "spi1_ss0_x";
885 function = "spi1";
886 bias-disable;
887 };
888 };
889
890 tdma_din0_pins: tdma_din0 {
891 mux {
892 groups = "tdma_din0";
893 function = "tdma";
894 bias-disable;
895 };
896 };
897
898 tdma_dout0_x14_pins: tdma_dout0_x14 {
899 mux {
900 groups = "tdma_dout0_x14";
901 function = "tdma";
902 bias-disable;
903 };
904 };
905
906 tdma_dout0_x15_pins: tdma_dout0_x15 {
907 mux {
908 groups = "tdma_dout0_x15";
909 function = "tdma";
910 bias-disable;
911 };
912 };
913
914 tdma_dout1_pins: tdma_dout1 {
915 mux {
916 groups = "tdma_dout1";
917 function = "tdma";
918 bias-disable;
919 };
920 };
921
922 tdma_din1_pins: tdma_din1 {
923 mux {
924 groups = "tdma_din1";
925 function = "tdma";
926 bias-disable;
927 };
928 };
929
930 tdma_fs_pins: tdma_fs {
931 mux {
932 groups = "tdma_fs";
933 function = "tdma";
934 bias-disable;
935 };
936 };
937
938 tdma_fs_slv_pins: tdma_fs_slv {
939 mux {
940 groups = "tdma_fs_slv";
941 function = "tdma";
942 bias-disable;
943 };
944 };
945
946 tdma_sclk_pins: tdma_sclk {
947 mux {
948 groups = "tdma_sclk";
949 function = "tdma";
950 bias-disable;
951 };
952 };
953
954 tdma_sclk_slv_pins: tdma_sclk_slv {
955 mux {
956 groups = "tdma_sclk_slv";
957 function = "tdma";
958 bias-disable;
959 };
960 };
961
962 tdmb_din0_pins: tdmb_din0 {
963 mux {
964 groups = "tdmb_din0";
965 function = "tdmb";
966 bias-disable;
967 };
968 };
969
970 tdmb_din1_pins: tdmb_din1 {
971 mux {
972 groups = "tdmb_din1";
973 function = "tdmb";
974 bias-disable;
975 };
976 };
977
978 tdmb_din2_pins: tdmb_din2 {
979 mux {
980 groups = "tdmb_din2";
981 function = "tdmb";
982 bias-disable;
983 };
984 };
985
986 tdmb_din3_pins: tdmb_din3 {
987 mux {
988 groups = "tdmb_din3";
989 function = "tdmb";
990 bias-disable;
991 };
992 };
993
994 tdmb_dout0_pins: tdmb_dout0 {
995 mux {
996 groups = "tdmb_dout0";
997 function = "tdmb";
998 bias-disable;
999 };
1000 };
1001
1002 tdmb_dout1_pins: tdmb_dout1 {
1003 mux {
1004 groups = "tdmb_dout1";
1005 function = "tdmb";
1006 bias-disable;
1007 };
1008 };
1009
1010 tdmb_dout2_pins: tdmb_dout2 {
1011 mux {
1012 groups = "tdmb_dout2";
1013 function = "tdmb";
1014 bias-disable;
1015 };
1016 };
1017
1018 tdmb_dout3_pins: tdmb_dout3 {
1019 mux {
1020 groups = "tdmb_dout3";
1021 function = "tdmb";
1022 bias-disable;
1023 };
1024 };
1025
1026 tdmb_fs_pins: tdmb_fs {
1027 mux {
1028 groups = "tdmb_fs";
1029 function = "tdmb";
1030 bias-disable;
1031 };
1032 };
1033
1034 tdmb_fs_slv_pins: tdmb_fs_slv {
1035 mux {
1036 groups = "tdmb_fs_slv";
1037 function = "tdmb";
1038 bias-disable;
1039 };
1040 };
1041
1042 tdmb_sclk_pins: tdmb_sclk {
1043 mux {
1044 groups = "tdmb_sclk";
1045 function = "tdmb";
1046 bias-disable;
1047 };
1048 };
1049
1050 tdmb_sclk_slv_pins: tdmb_sclk_slv {
1051 mux {
1052 groups = "tdmb_sclk_slv";
1053 function = "tdmb";
1054 bias-disable;
1055 };
1056 };
1057
1058 tdmc_fs_pins: tdmc_fs {
1059 mux {
1060 groups = "tdmc_fs";
1061 function = "tdmc";
1062 bias-disable;
1063 };
1064 };
1065
1066 tdmc_fs_slv_pins: tdmc_fs_slv {
1067 mux {
1068 groups = "tdmc_fs_slv";
1069 function = "tdmc";
1070 bias-disable;
1071 };
1072 };
1073
1074 tdmc_sclk_pins: tdmc_sclk {
1075 mux {
1076 groups = "tdmc_sclk";
1077 function = "tdmc";
1078 bias-disable;
1079 };
1080 };
1081
1082 tdmc_sclk_slv_pins: tdmc_sclk_slv {
1083 mux {
1084 groups = "tdmc_sclk_slv";
1085 function = "tdmc";
1086 bias-disable;
1087 };
1088 };
1089
1090 tdmc_din0_pins: tdmc_din0 {
1091 mux {
1092 groups = "tdmc_din0";
1093 function = "tdmc";
1094 bias-disable;
1095 };
1096 };
1097
1098 tdmc_din1_pins: tdmc_din1 {
1099 mux {
1100 groups = "tdmc_din1";
1101 function = "tdmc";
1102 bias-disable;
1103 };
1104 };
1105
1106 tdmc_din2_pins: tdmc_din2 {
1107 mux {
1108 groups = "tdmc_din2";
1109 function = "tdmc";
1110 bias-disable;
1111 };
1112 };
1113
1114 tdmc_din3_pins: tdmc_din3 {
1115 mux {
1116 groups = "tdmc_din3";
1117 function = "tdmc";
1118 bias-disable;
1119 };
1120 };
1121
1122 tdmc_dout0_pins: tdmc_dout0 {
1123 mux {
1124 groups = "tdmc_dout0";
1125 function = "tdmc";
1126 bias-disable;
1127 };
1128 };
1129
1130 tdmc_dout1_pins: tdmc_dout1 {
1131 mux {
1132 groups = "tdmc_dout1";
1133 function = "tdmc";
1134 bias-disable;
1135 };
1136 };
1137
1138 tdmc_dout2_pins: tdmc_dout2 {
1139 mux {
1140 groups = "tdmc_dout2";
1141 function = "tdmc";
1142 bias-disable;
1143 };
1144 };
1145
1146 tdmc_dout3_pins: tdmc_dout3 {
1147 mux {
1148 groups = "tdmc_dout3";
1149 function = "tdmc";
1150 bias-disable;
1151 };
1152 };
1153
1154 uart_a_pins: uart_a {
1155 mux {
1156 groups = "uart_tx_a",
1157 "uart_rx_a";
1158 function = "uart_a";
1159 bias-disable;
1160 };
1161 };
1162
1163 uart_a_cts_rts_pins: uart_a_cts_rts {
1164 mux {
1165 groups = "uart_cts_a",
1166 "uart_rts_a";
1167 function = "uart_a";
1168 bias-disable;
1169 };
1170 };
1171
1172 uart_b_x_pins: uart_b_x {
1173 mux {
1174 groups = "uart_tx_b_x",
1175 "uart_rx_b_x";
1176 function = "uart_b";
1177 bias-disable;
1178 };
1179 };
1180
1181 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1182 mux {
1183 groups = "uart_cts_b_x",
1184 "uart_rts_b_x";
1185 function = "uart_b";
1186 bias-disable;
1187 };
1188 };
1189
1190 uart_b_z_pins: uart_b_z {
1191 mux {
1192 groups = "uart_tx_b_z",
1193 "uart_rx_b_z";
1194 function = "uart_b";
1195 bias-disable;
1196 };
1197 };
1198
1199 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1200 mux {
1201 groups = "uart_cts_b_z",
1202 "uart_rts_b_z";
1203 function = "uart_b";
1204 bias-disable;
1205 };
1206 };
1207
1208 uart_ao_b_z_pins: uart_ao_b_z {
1209 mux {
1210 groups = "uart_ao_tx_b_z",
1211 "uart_ao_rx_b_z";
1212 function = "uart_ao_b_z";
1213 bias-disable;
1214 };
1215 };
1216
1217 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1218 mux {
1219 groups = "uart_ao_cts_b_z",
1220 "uart_ao_rts_b_z";
1221 function = "uart_ao_b_z";
1222 bias-disable;
1223 };
1224 };
1225 };
1226 };
1227
1228 hiubus: bus@ff63c000 {
1229 compatible = "simple-bus";
1230 reg = <0x0 0xff63c000 0x0 0x1c00>;
1231 #address-cells = <2>;
1232 #size-cells = <2>;
1233 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1234
1235 sysctrl: system-controller@0 {
1236 compatible = "amlogic,meson-axg-hhi-sysctrl",
1237 "simple-mfd", "syscon";
1238 reg = <0 0 0 0x400>;
1239
1240 clkc: clock-controller {
1241 compatible = "amlogic,axg-clkc";
1242 #clock-cells = <1>;
1243 clocks = <&xtal>;
1244 clock-names = "xtal";
1245 };
1246
1247 pwrc: power-controller {
1248 compatible = "amlogic,meson-axg-pwrc";
1249 #power-domain-cells = <1>;
1250 amlogic,ao-sysctrl = <&sysctrl_AO>;
1251 resets = <&reset RESET_VIU>,
1252 <&reset RESET_VENC>,
1253 <&reset RESET_VCBUS>,
1254 <&reset RESET_VENCL>,
1255 <&reset RESET_VID_LOCK>;
1256 reset-names = "viu", "venc", "vcbus",
1257 "vencl", "vid_lock";
1258 clocks = <&clkc CLKID_VPU>,
1259 <&clkc CLKID_VAPB>;
1260 clock-names = "vpu", "vapb";
1261 /*
1262 * VPU clocking is provided by two identical clock paths
1263 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1264 * free mux to safely change frequency while running.
1265 * Same for VAPB but with a final gate after the glitch free mux.
1266 */
1267 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1268 <&clkc CLKID_VPU_0>,
1269 <&clkc CLKID_VPU>, /* Glitch free mux */
1270 <&clkc CLKID_VAPB_0_SEL>,
1271 <&clkc CLKID_VAPB_0>,
1272 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1273 assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1274 <0>, /* Do Nothing */
1275 <&clkc CLKID_VPU_0>,
1276 <&clkc CLKID_FCLK_DIV4>,
1277 <0>, /* Do Nothing */
1278 <&clkc CLKID_VAPB_0>;
1279 assigned-clock-rates = <0>, /* Do Nothing */
1280 <250000000>,
1281 <0>, /* Do Nothing */
1282 <0>, /* Do Nothing */
1283 <250000000>,
1284 <0>; /* Do Nothing */
1285 };
1286
1287 mipi_pcie_analog_dphy: phy {
1288 compatible = "amlogic,axg-mipi-pcie-analog-phy";
1289 #phy-cells = <0>;
1290 status = "disabled";
1291 };
1292 };
1293 };
1294
1295 mailbox: mailbox@ff63c404 {
1296 compatible = "amlogic,meson-gxbb-mhu";
1297 reg = <0 0xff63c404 0 0x4c>;
1298 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1299 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1300 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1301 #mbox-cells = <1>;
1302 };
1303
1304 mipi_dphy: phy@ff640000 {
1305 compatible = "amlogic,axg-mipi-dphy";
1306 reg = <0x0 0xff640000 0x0 0x100>;
1307 clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1308 clock-names = "pclk";
1309 resets = <&reset RESET_MIPI_PHY>;
1310 reset-names = "phy";
1311 phys = <&mipi_pcie_analog_dphy>;
1312 phy-names = "analog";
1313 #phy-cells = <0>;
1314 status = "disabled";
1315 };
1316
1317 audio: bus@ff642000 {
1318 compatible = "simple-bus";
1319 reg = <0x0 0xff642000 0x0 0x2000>;
1320 #address-cells = <2>;
1321 #size-cells = <2>;
1322 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1323
1324 clkc_audio: clock-controller@0 {
1325 compatible = "amlogic,axg-audio-clkc";
1326 reg = <0x0 0x0 0x0 0xb4>;
1327 #clock-cells = <1>;
1328
1329 clocks = <&clkc CLKID_AUDIO>,
1330 <&clkc CLKID_MPLL0>,
1331 <&clkc CLKID_MPLL1>,
1332 <&clkc CLKID_MPLL2>,
1333 <&clkc CLKID_MPLL3>,
1334 <&clkc CLKID_HIFI_PLL>,
1335 <&clkc CLKID_FCLK_DIV3>,
1336 <&clkc CLKID_FCLK_DIV4>,
1337 <&clkc CLKID_GP0_PLL>;
1338 clock-names = "pclk",
1339 "mst_in0",
1340 "mst_in1",
1341 "mst_in2",
1342 "mst_in3",
1343 "mst_in4",
1344 "mst_in5",
1345 "mst_in6",
1346 "mst_in7";
1347
1348 resets = <&reset RESET_AUDIO>;
1349 };
1350
1351 toddr_a: audio-controller@100 {
1352 compatible = "amlogic,axg-toddr";
1353 reg = <0x0 0x100 0x0 0x2c>;
1354 #sound-dai-cells = <0>;
1355 sound-name-prefix = "TODDR_A";
1356 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1357 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1358 resets = <&arb AXG_ARB_TODDR_A>;
1359 amlogic,fifo-depth = <512>;
1360 status = "disabled";
1361 };
1362
1363 toddr_b: audio-controller@140 {
1364 compatible = "amlogic,axg-toddr";
1365 reg = <0x0 0x140 0x0 0x2c>;
1366 #sound-dai-cells = <0>;
1367 sound-name-prefix = "TODDR_B";
1368 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1369 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1370 resets = <&arb AXG_ARB_TODDR_B>;
1371 amlogic,fifo-depth = <256>;
1372 status = "disabled";
1373 };
1374
1375 toddr_c: audio-controller@180 {
1376 compatible = "amlogic,axg-toddr";
1377 reg = <0x0 0x180 0x0 0x2c>;
1378 #sound-dai-cells = <0>;
1379 sound-name-prefix = "TODDR_C";
1380 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1381 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1382 resets = <&arb AXG_ARB_TODDR_C>;
1383 amlogic,fifo-depth = <256>;
1384 status = "disabled";
1385 };
1386
1387 frddr_a: audio-controller@1c0 {
1388 compatible = "amlogic,axg-frddr";
1389 reg = <0x0 0x1c0 0x0 0x2c>;
1390 #sound-dai-cells = <0>;
1391 sound-name-prefix = "FRDDR_A";
1392 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1393 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1394 resets = <&arb AXG_ARB_FRDDR_A>;
1395 amlogic,fifo-depth = <512>;
1396 status = "disabled";
1397 };
1398
1399 frddr_b: audio-controller@200 {
1400 compatible = "amlogic,axg-frddr";
1401 reg = <0x0 0x200 0x0 0x2c>;
1402 #sound-dai-cells = <0>;
1403 sound-name-prefix = "FRDDR_B";
1404 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1405 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1406 resets = <&arb AXG_ARB_FRDDR_B>;
1407 amlogic,fifo-depth = <256>;
1408 status = "disabled";
1409 };
1410
1411 frddr_c: audio-controller@240 {
1412 compatible = "amlogic,axg-frddr";
1413 reg = <0x0 0x240 0x0 0x2c>;
1414 #sound-dai-cells = <0>;
1415 sound-name-prefix = "FRDDR_C";
1416 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1417 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1418 resets = <&arb AXG_ARB_FRDDR_C>;
1419 amlogic,fifo-depth = <256>;
1420 status = "disabled";
1421 };
1422
1423 arb: reset-controller@280 {
1424 compatible = "amlogic,meson-axg-audio-arb";
1425 reg = <0x0 0x280 0x0 0x4>;
1426 #reset-cells = <1>;
1427 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1428 };
1429
1430 tdmin_a: audio-controller@300 {
1431 compatible = "amlogic,axg-tdmin";
1432 reg = <0x0 0x300 0x0 0x40>;
1433 sound-name-prefix = "TDMIN_A";
1434 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1435 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1436 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1437 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1438 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1439 clock-names = "pclk", "sclk", "sclk_sel",
1440 "lrclk", "lrclk_sel";
1441 status = "disabled";
1442 };
1443
1444 tdmin_b: audio-controller@340 {
1445 compatible = "amlogic,axg-tdmin";
1446 reg = <0x0 0x340 0x0 0x40>;
1447 sound-name-prefix = "TDMIN_B";
1448 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1449 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1450 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1451 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1452 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1453 clock-names = "pclk", "sclk", "sclk_sel",
1454 "lrclk", "lrclk_sel";
1455 status = "disabled";
1456 };
1457
1458 tdmin_c: audio-controller@380 {
1459 compatible = "amlogic,axg-tdmin";
1460 reg = <0x0 0x380 0x0 0x40>;
1461 sound-name-prefix = "TDMIN_C";
1462 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1463 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1464 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1465 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1466 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1467 clock-names = "pclk", "sclk", "sclk_sel",
1468 "lrclk", "lrclk_sel";
1469 status = "disabled";
1470 };
1471
1472 tdmin_lb: audio-controller@3c0 {
1473 compatible = "amlogic,axg-tdmin";
1474 reg = <0x0 0x3c0 0x0 0x40>;
1475 sound-name-prefix = "TDMIN_LB";
1476 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1477 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1478 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1479 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1480 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1481 clock-names = "pclk", "sclk", "sclk_sel",
1482 "lrclk", "lrclk_sel";
1483 status = "disabled";
1484 };
1485
1486 spdifin: audio-controller@400 {
1487 compatible = "amlogic,axg-spdifin";
1488 reg = <0x0 0x400 0x0 0x30>;
1489 #sound-dai-cells = <0>;
1490 sound-name-prefix = "SPDIFIN";
1491 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1492 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1493 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1494 clock-names = "pclk", "refclk";
1495 status = "disabled";
1496 };
1497
1498 spdifout: audio-controller@480 {
1499 compatible = "amlogic,axg-spdifout";
1500 reg = <0x0 0x480 0x0 0x50>;
1501 #sound-dai-cells = <0>;
1502 sound-name-prefix = "SPDIFOUT";
1503 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1504 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1505 clock-names = "pclk", "mclk";
1506 status = "disabled";
1507 };
1508
1509 tdmout_a: audio-controller@500 {
1510 compatible = "amlogic,axg-tdmout";
1511 reg = <0x0 0x500 0x0 0x40>;
1512 sound-name-prefix = "TDMOUT_A";
1513 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1514 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1515 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1516 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1517 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1518 clock-names = "pclk", "sclk", "sclk_sel",
1519 "lrclk", "lrclk_sel";
1520 status = "disabled";
1521 };
1522
1523 tdmout_b: audio-controller@540 {
1524 compatible = "amlogic,axg-tdmout";
1525 reg = <0x0 0x540 0x0 0x40>;
1526 sound-name-prefix = "TDMOUT_B";
1527 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1528 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1529 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1530 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1531 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1532 clock-names = "pclk", "sclk", "sclk_sel",
1533 "lrclk", "lrclk_sel";
1534 status = "disabled";
1535 };
1536
1537 tdmout_c: audio-controller@580 {
1538 compatible = "amlogic,axg-tdmout";
1539 reg = <0x0 0x580 0x0 0x40>;
1540 sound-name-prefix = "TDMOUT_C";
1541 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1542 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1543 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1544 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1545 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1546 clock-names = "pclk", "sclk", "sclk_sel",
1547 "lrclk", "lrclk_sel";
1548 status = "disabled";
1549 };
1550 };
1551
1552 aobus: bus@ff800000 {
1553 compatible = "simple-bus";
1554 reg = <0x0 0xff800000 0x0 0x100000>;
1555 #address-cells = <2>;
1556 #size-cells = <2>;
1557 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1558
1559 sysctrl_AO: sys-ctrl@0 {
1560 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1561 reg = <0x0 0x0 0x0 0x100>;
1562
1563 clkc_AO: clock-controller {
1564 compatible = "amlogic,meson-axg-aoclkc";
1565 #clock-cells = <1>;
1566 #reset-cells = <1>;
1567 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1568 clock-names = "xtal", "mpeg-clk";
1569 };
1570 };
1571
1572 pinctrl_aobus: pinctrl@14 {
1573 compatible = "amlogic,meson-axg-aobus-pinctrl";
1574 #address-cells = <2>;
1575 #size-cells = <2>;
1576 ranges;
1577
1578 gpio_ao: bank@14 {
1579 reg = <0x0 0x00014 0x0 0x8>,
1580 <0x0 0x0002c 0x0 0x4>,
1581 <0x0 0x00024 0x0 0x8>;
1582 reg-names = "mux", "pull", "gpio";
1583 gpio-controller;
1584 #gpio-cells = <2>;
1585 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1586 };
1587
1588 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1589 mux {
1590 groups = "i2c_ao_sck_4";
1591 function = "i2c_ao";
1592 bias-disable;
1593 };
1594 };
1595
1596 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1597 mux {
1598 groups = "i2c_ao_sck_8";
1599 function = "i2c_ao";
1600 bias-disable;
1601 };
1602 };
1603
1604 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1605 mux {
1606 groups = "i2c_ao_sck_10";
1607 function = "i2c_ao";
1608 bias-disable;
1609 };
1610 };
1611
1612 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1613 mux {
1614 groups = "i2c_ao_sda_5";
1615 function = "i2c_ao";
1616 bias-disable;
1617 };
1618 };
1619
1620 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1621 mux {
1622 groups = "i2c_ao_sda_9";
1623 function = "i2c_ao";
1624 bias-disable;
1625 };
1626 };
1627
1628 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1629 mux {
1630 groups = "i2c_ao_sda_11";
1631 function = "i2c_ao";
1632 bias-disable;
1633 };
1634 };
1635
1636 remote_input_ao_pins: remote_input_ao {
1637 mux {
1638 groups = "remote_input_ao";
1639 function = "remote_input_ao";
1640 bias-disable;
1641 };
1642 };
1643
1644 uart_ao_a_pins: uart_ao_a {
1645 mux {
1646 groups = "uart_ao_tx_a",
1647 "uart_ao_rx_a";
1648 function = "uart_ao_a";
1649 bias-disable;
1650 };
1651 };
1652
1653 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1654 mux {
1655 groups = "uart_ao_cts_a",
1656 "uart_ao_rts_a";
1657 function = "uart_ao_a";
1658 bias-disable;
1659 };
1660 };
1661
1662 uart_ao_b_pins: uart_ao_b {
1663 mux {
1664 groups = "uart_ao_tx_b",
1665 "uart_ao_rx_b";
1666 function = "uart_ao_b";
1667 bias-disable;
1668 };
1669 };
1670
1671 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1672 mux {
1673 groups = "uart_ao_cts_b",
1674 "uart_ao_rts_b";
1675 function = "uart_ao_b";
1676 bias-disable;
1677 };
1678 };
1679 };
1680
1681 sec_AO: ao-secure@140 {
1682 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1683 reg = <0x0 0x140 0x0 0x140>;
1684 amlogic,has-chip-id;
1685 };
1686
1687 pwm_AO_cd: pwm@2000 {
1688 compatible = "amlogic,meson-axg-ao-pwm";
1689 reg = <0x0 0x02000 0x0 0x20>;
1690 #pwm-cells = <3>;
1691 status = "disabled";
1692 };
1693
1694 uart_AO: serial@3000 {
1695 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1696 reg = <0x0 0x3000 0x0 0x18>;
1697 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1698 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1699 clock-names = "xtal", "pclk", "baud";
1700 status = "disabled";
1701 };
1702
1703 uart_AO_B: serial@4000 {
1704 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1705 reg = <0x0 0x4000 0x0 0x18>;
1706 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1707 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1708 clock-names = "xtal", "pclk", "baud";
1709 status = "disabled";
1710 };
1711
1712 i2c_AO: i2c@5000 {
1713 compatible = "amlogic,meson-axg-i2c";
1714 reg = <0x0 0x05000 0x0 0x20>;
1715 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1716 clocks = <&clkc CLKID_AO_I2C>;
1717 #address-cells = <1>;
1718 #size-cells = <0>;
1719 status = "disabled";
1720 };
1721
1722 pwm_AO_ab: pwm@7000 {
1723 compatible = "amlogic,meson-axg-ao-pwm";
1724 reg = <0x0 0x07000 0x0 0x20>;
1725 #pwm-cells = <3>;
1726 status = "disabled";
1727 };
1728
1729 ir: ir@8000 {
1730 compatible = "amlogic,meson-gxbb-ir";
1731 reg = <0x0 0x8000 0x0 0x20>;
1732 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1733 status = "disabled";
1734 };
1735
1736 saradc: adc@9000 {
1737 compatible = "amlogic,meson-axg-saradc",
1738 "amlogic,meson-saradc";
1739 reg = <0x0 0x9000 0x0 0x38>;
1740 #io-channel-cells = <1>;
1741 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1742 clocks = <&xtal>,
1743 <&clkc_AO CLKID_AO_SAR_ADC>,
1744 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1745 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1746 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1747 status = "disabled";
1748 };
1749 };
1750
1751 ge2d: ge2d@ff940000 {
1752 compatible = "amlogic,axg-ge2d";
1753 reg = <0x0 0xff940000 0x0 0x10000>;
1754 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1755 clocks = <&clkc CLKID_VAPB>;
1756 resets = <&reset RESET_GE2D>;
1757 };
1758
1759 gic: interrupt-controller@ffc01000 {
1760 compatible = "arm,gic-400";
1761 reg = <0x0 0xffc01000 0 0x1000>,
1762 <0x0 0xffc02000 0 0x2000>,
1763 <0x0 0xffc04000 0 0x2000>,
1764 <0x0 0xffc06000 0 0x2000>;
1765 interrupt-controller;
1766 interrupts = <GIC_PPI 9
1767 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1768 #interrupt-cells = <3>;
1769 #address-cells = <0>;
1770 };
1771
1772 cbus: bus@ffd00000 {
1773 compatible = "simple-bus";
1774 reg = <0x0 0xffd00000 0x0 0x25000>;
1775 #address-cells = <2>;
1776 #size-cells = <2>;
1777 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1778
1779 reset: reset-controller@1004 {
1780 compatible = "amlogic,meson-axg-reset";
1781 reg = <0x0 0x01004 0x0 0x9c>;
1782 #reset-cells = <1>;
1783 };
1784
1785 gpio_intc: interrupt-controller@f080 {
1786 compatible = "amlogic,meson-axg-gpio-intc",
1787 "amlogic,meson-gpio-intc";
1788 reg = <0x0 0xf080 0x0 0x10>;
1789 interrupt-controller;
1790 #interrupt-cells = <2>;
1791 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1792 };
1793
1794 watchdog@f0d0 {
1795 compatible = "amlogic,meson-gxbb-wdt";
1796 reg = <0x0 0xf0d0 0x0 0x10>;
1797 clocks = <&xtal>;
1798 };
1799
1800 pwm_ab: pwm@1b000 {
1801 compatible = "amlogic,meson-axg-ee-pwm";
1802 reg = <0x0 0x1b000 0x0 0x20>;
1803 #pwm-cells = <3>;
1804 status = "disabled";
1805 };
1806
1807 pwm_cd: pwm@1a000 {
1808 compatible = "amlogic,meson-axg-ee-pwm";
1809 reg = <0x0 0x1a000 0x0 0x20>;
1810 #pwm-cells = <3>;
1811 status = "disabled";
1812 };
1813
1814 spicc0: spi@13000 {
1815 compatible = "amlogic,meson-axg-spicc";
1816 reg = <0x0 0x13000 0x0 0x3c>;
1817 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1818 clocks = <&clkc CLKID_SPICC0>;
1819 clock-names = "core";
1820 #address-cells = <1>;
1821 #size-cells = <0>;
1822 status = "disabled";
1823 };
1824
1825 spicc1: spi@15000 {
1826 compatible = "amlogic,meson-axg-spicc";
1827 reg = <0x0 0x15000 0x0 0x3c>;
1828 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1829 clocks = <&clkc CLKID_SPICC1>;
1830 clock-names = "core";
1831 #address-cells = <1>;
1832 #size-cells = <0>;
1833 status = "disabled";
1834 };
1835
1836 clk_msr: clock-measure@18000 {
1837 compatible = "amlogic,meson-axg-clk-measure";
1838 reg = <0x0 0x18000 0x0 0x10>;
1839 };
1840
1841 i2c3: i2c@1c000 {
1842 compatible = "amlogic,meson-axg-i2c";
1843 reg = <0x0 0x1c000 0x0 0x20>;
1844 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1845 clocks = <&clkc CLKID_I2C>;
1846 #address-cells = <1>;
1847 #size-cells = <0>;
1848 status = "disabled";
1849 };
1850
1851 i2c2: i2c@1d000 {
1852 compatible = "amlogic,meson-axg-i2c";
1853 reg = <0x0 0x1d000 0x0 0x20>;
1854 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1855 clocks = <&clkc CLKID_I2C>;
1856 #address-cells = <1>;
1857 #size-cells = <0>;
1858 status = "disabled";
1859 };
1860
1861 i2c1: i2c@1e000 {
1862 compatible = "amlogic,meson-axg-i2c";
1863 reg = <0x0 0x1e000 0x0 0x20>;
1864 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1865 clocks = <&clkc CLKID_I2C>;
1866 #address-cells = <1>;
1867 #size-cells = <0>;
1868 status = "disabled";
1869 };
1870
1871 i2c0: i2c@1f000 {
1872 compatible = "amlogic,meson-axg-i2c";
1873 reg = <0x0 0x1f000 0x0 0x20>;
1874 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1875 clocks = <&clkc CLKID_I2C>;
1876 #address-cells = <1>;
1877 #size-cells = <0>;
1878 status = "disabled";
1879 };
1880
1881 uart_B: serial@23000 {
1882 compatible = "amlogic,meson-gx-uart";
1883 reg = <0x0 0x23000 0x0 0x18>;
1884 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1885 status = "disabled";
1886 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1887 clock-names = "xtal", "pclk", "baud";
1888 };
1889
1890 uart_A: serial@24000 {
1891 compatible = "amlogic,meson-gx-uart";
1892 reg = <0x0 0x24000 0x0 0x18>;
1893 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1894 status = "disabled";
1895 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1896 clock-names = "xtal", "pclk", "baud";
1897 fifo-size = <128>;
1898 };
1899 };
1900
1901 apb: bus@ffe00000 {
1902 compatible = "simple-bus";
1903 reg = <0x0 0xffe00000 0x0 0x200000>;
1904 #address-cells = <2>;
1905 #size-cells = <2>;
1906 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1907
1908 sd_emmc_b: mmc@5000 {
1909 compatible = "amlogic,meson-axg-mmc";
1910 reg = <0x0 0x5000 0x0 0x800>;
1911 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1912 status = "disabled";
1913 clocks = <&clkc CLKID_SD_EMMC_B>,
1914 <&clkc CLKID_SD_EMMC_B_CLK0>,
1915 <&clkc CLKID_FCLK_DIV2>;
1916 clock-names = "core", "clkin0", "clkin1";
1917 resets = <&reset RESET_SD_EMMC_B>;
1918 };
1919
1920 sd_emmc_c: mmc@7000 {
1921 compatible = "amlogic,meson-axg-mmc";
1922 reg = <0x0 0x7000 0x0 0x800>;
1923 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1924 status = "disabled";
1925 clocks = <&clkc CLKID_SD_EMMC_C>,
1926 <&clkc CLKID_SD_EMMC_C_CLK0>,
1927 <&clkc CLKID_FCLK_DIV2>;
1928 clock-names = "core", "clkin0", "clkin1";
1929 resets = <&reset RESET_SD_EMMC_C>;
1930 };
1931
1932 nfc: nand-controller@7800 {
1933 compatible = "amlogic,meson-axg-nfc";
1934 reg = <0x0 0x7800 0x0 0x100>,
1935 <0x0 0x7000 0x0 0x800>;
1936 reg-names = "nfc", "emmc";
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]1937 pinctrl-0 = <&nand_all_pins>;
1938 pinctrl-names = "default";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1939 #address-cells = <1>;
1940 #size-cells = <0>;
1941 interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
1942 clocks = <&clkc CLKID_SD_EMMC_C>,
1943 <&clkc CLKID_FCLK_DIV2>;
1944 clock-names = "core", "device";
1945 };
1946
1947 usb2_phy1: phy@9020 {
1948 compatible = "amlogic,meson-gxl-usb2-phy";
1949 #phy-cells = <0>;
1950 reg = <0x0 0x9020 0x0 0x20>;
1951 clocks = <&clkc CLKID_USB>;
1952 clock-names = "phy";
1953 resets = <&reset RESET_USB_OTG>;
1954 reset-names = "phy";
1955 };
1956 };
1957
1958 sram: sram@fffc0000 {
1959 compatible = "mmio-sram";
1960 reg = <0x0 0xfffc0000 0x0 0x20000>;
1961 #address-cells = <1>;
1962 #size-cells = <1>;
1963 ranges = <0 0x0 0xfffc0000 0x20000>;
1964
1965 cpu_scp_lpri: scp-sram@13000 {
1966 compatible = "amlogic,meson-axg-scp-shmem";
1967 reg = <0x13000 0x400>;
1968 };
1969
1970 cpu_scp_hpri: scp-sram@13400 {
1971 compatible = "amlogic,meson-axg-scp-shmem";
1972 reg = <0x13400 0x400>;
1973 };
1974 };
1975 };
1976
1977 timer {
1978 compatible = "arm,armv8-timer";
1979 interrupts = <GIC_PPI 13
1980 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1981 <GIC_PPI 14
1982 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1983 <GIC_PPI 11
1984 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1985 <GIC_PPI 10
1986 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1987 };
1988
1989 xtal: xtal-clk {
1990 compatible = "fixed-clock";
1991 clock-frequency = <24000000>;
1992 clock-output-names = "xtal";
1993 #clock-cells = <0>;
1994 };
1995};