Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm / ti / omap / omap3-cm-t3x.dtsi
blob: 950a29f9b4a0b724012be0972b34ba3ff2e6ccea [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Common support for CompuLab CM-T3x CoMs
4 */
5
6/ {
7
8 memory@80000000 {
9 device_type = "memory";
10 reg = <0x80000000 0x10000000>; /* 256 MB */
11 };
12
13 leds {
14 compatible = "gpio-leds";
15 pinctrl-names = "default";
16 pinctrl-0 = <&green_led_pins>;
17 ledb {
18 label = "cm-t3x:green";
19 gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* gpio186 */
20 linux,default-trigger = "heartbeat";
21 };
22 };
23
24 /* HS USB Port 1 Power */
25 hsusb1_power: hsusb1_power_reg {
26 compatible = "regulator-fixed";
27 regulator-name = "hsusb1_vbus";
28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <3300000>;
30 startup-delay-us = <70000>;
31 };
32
33 /* HS USB Port 2 Power */
34 hsusb2_power: hsusb2_power_reg {
35 compatible = "regulator-fixed";
36 regulator-name = "hsusb2_vbus";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 startup-delay-us = <70000>;
40 };
41
42 /* HS USB Host PHY on PORT 1 */
43 hsusb1_phy: hsusb1_phy {
44 compatible = "usb-nop-xceiv";
45 vcc-supply = <&hsusb1_power>;
46 #phy-cells = <0>;
47 };
48
49 /* HS USB Host PHY on PORT 2 */
50 hsusb2_phy: hsusb2-phy-pins {
51 compatible = "usb-nop-xceiv";
52 vcc-supply = <&hsusb2_power>;
53 #phy-cells = <0>;
54 };
55
56 ads7846reg: ads7846-reg {
57 compatible = "regulator-fixed";
58 regulator-name = "ads7846-reg";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 };
62
63 tv0: svideo-connector {
64 compatible = "svideo-connector";
65 label = "tv";
66
67 port {
68 tv_connector_in: endpoint {
69 remote-endpoint = <&venc_out>;
70 };
71 };
72 };
73};
74
75&omap3_pmx_core {
76
77 uart3_pins: uart3-pins {
78 pinctrl-single,pins = <
79 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
80 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
81 >;
82 };
83
84 mmc1_pins: mmc1-pins {
85 pinctrl-single,pins = <
86 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
87 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
88 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
89 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
90 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
91 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
92 >;
93 };
94
95 green_led_pins: green-led-pins {
96 pinctrl-single,pins = <
97 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
98 >;
99 };
100
101 dss_dpi_pins_common: dss-dpi-common-pins {
102 pinctrl-single,pins = <
103 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
104 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
105 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
106 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
107
108 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
109 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
110 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
111 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
112 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
113 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
114 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
115 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
116 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
117 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
118 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
119 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
120 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
121 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
122 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
123 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
124 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
125 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
126 >;
127 };
128
129 dss_dpi_pins_cm_t35x: dss-dpi-cm-t35x-pins {
130 pinctrl-single,pins = <
131 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
132 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
133 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
134 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
135 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
136 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
137 >;
138 };
139
140 ads7846_pins: ads7846-pins {
141 pinctrl-single,pins = <
142 OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
143 >;
144 };
145
146 mcspi1_pins: mcspi1-pins {
147 pinctrl-single,pins = <
148 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */
149 OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */
150 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */
151 OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */
152 >;
153 };
154
155 i2c1_pins: i2c1-pins {
156 pinctrl-single,pins = <
157 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
158 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
159 >;
160 };
161
162 mcbsp2_pins: mcbsp2-pins {
163 pinctrl-single,pins = <
164 OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
165 OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
166 OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
167 OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
168 >;
169 };
170};
171
172&uart3 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&uart3_pins>;
175};
176
177&mmc1 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&mmc1_pins>;
180 bus-width = <4>;
181};
182
183&mmc3 {
184 status = "disabled";
185};
186
187&i2c1 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&i2c1_pins>;
190
191 clock-frequency = <400000>;
192
193 at24@50 {
194 compatible = "atmel,24c02";
195 pagesize = <16>;
196 reg = <0x50>;
197 };
198};
199
200&i2c3 {
201 clock-frequency = <400000>;
202};
203
204&usbhshost {
205 port1-mode = "ehci-phy";
206 port2-mode = "ehci-phy";
207};
208
209&usbhsehci {
210 phys = <&hsusb1_phy &hsusb2_phy>;
211};
212
213&mcspi1 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&mcspi1_pins>;
216
217 /* touch controller */
218 ads7846@0 {
219 pinctrl-names = "default";
220 pinctrl-0 = <&ads7846_pins>;
221
222 compatible = "ti,ads7846";
223 vcc-supply = <&ads7846reg>;
224
225 reg = <0>; /* CS0 */
226 spi-max-frequency = <1500000>;
227
228 interrupt-parent = <&gpio2>;
229 interrupts = <25 0>; /* gpio_57 */
230 pendown-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
231
232 ti,x-min = /bits/ 16 <0x0>;
233 ti,x-max = /bits/ 16 <0x0fff>;
234 ti,y-min = /bits/ 16 <0x0>;
235 ti,y-max = /bits/ 16 <0x0fff>;
236
237 ti,x-plate-ohms = /bits/ 16 <180>;
238 ti,pressure-max = /bits/ 16 <255>;
239
240 ti,debounce-max = /bits/ 16 <30>;
241 ti,debounce-tol = /bits/ 16 <10>;
242 ti,debounce-rep = /bits/ 16 <1>;
243
244 wakeup-source;
245 };
246};
247
248&venc {
249 status = "okay";
250
251 port {
252 venc_out: endpoint {
253 remote-endpoint = <&tv_connector_in>;
254 ti,channels = <2>;
255 };
256 };
257};
258
259&mcbsp2 {
260 status = "okay";
261
262 pinctrl-names = "default";
263 pinctrl-0 = <&mcbsp2_pins>;
264};
265
266&gpmc {
267 ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
268
269 nand@0,0 {
270 compatible = "ti,omap2-nand";
271 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
272 interrupt-parent = <&gpmc>;
273 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
274 <1 IRQ_TYPE_NONE>; /* termcount */
275 nand-bus-width = <8>;
276 gpmc,device-width = <1>;
277 ti,nand-ecc-opt = "sw";
278
279 gpmc,cs-on-ns = <0>;
280 gpmc,cs-rd-off-ns = <120>;
281 gpmc,cs-wr-off-ns = <120>;
282
283 gpmc,adv-on-ns = <0>;
284 gpmc,adv-rd-off-ns = <120>;
285 gpmc,adv-wr-off-ns = <120>;
286
287 gpmc,we-on-ns = <6>;
288 gpmc,we-off-ns = <90>;
289
290 gpmc,oe-on-ns = <6>;
291 gpmc,oe-off-ns = <90>;
292
293 gpmc,page-burst-access-ns = <6>;
294 gpmc,access-ns = <72>;
295 gpmc,cycle2cycle-delay-ns = <60>;
296
297 gpmc,rd-cycle-ns = <120>;
298 gpmc,wr-cycle-ns = <120>;
299 gpmc,wr-access-ns = <186>;
300 gpmc,wr-data-mux-bus-ns = <90>;
301
302 #address-cells = <1>;
303 #size-cells = <1>;
304
305 partition@0 {
306 label = "xloader";
307 reg = <0 0x80000>;
308 };
309 partition@80000 {
310 label = "uboot";
311 reg = <0x80000 0x1e0000>;
312 };
313 partition@260000 {
314 label = "uboot environment";
315 reg = <0x260000 0x40000>;
316 };
317 partition@2a0000 {
318 label = "linux";
319 reg = <0x2a0000 0x400000>;
320 };
321 partition@6a0000 {
322 label = "rootfs";
323 reg = <0x6a0000 0x1f880000>;
324 };
325 };
326};