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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm / nxp / vf / vfxxx.dtsi
blob: acccf9a3c898e0fb9eba1ef4aa320908d06a6b64 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include "vf610-pinfunc.h"
6#include <dt-bindings/clock/vf610-clock.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 aliases {
12 can0 = &can0;
13 can1 = &can1;
14 ethernet0 = &fec0;
15 ethernet1 = &fec1;
16 serial0 = &uart0;
17 serial1 = &uart1;
18 serial2 = &uart2;
19 serial3 = &uart3;
20 serial4 = &uart4;
21 serial5 = &uart5;
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 usbphy0 = &usbphy0;
28 usbphy1 = &usbphy1;
29 };
30
31 fxosc: fxosc {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
35 };
36
37 sxosc: sxosc {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <32768>;
41 };
42
43 reboot: syscon-reboot {
44 compatible = "syscon-reboot";
45 regmap = <&src>;
46 offset = <0x0>;
47 mask = <0x1000>;
48 };
49
50 tempsensor: iio-hwmon {
51 compatible = "iio-hwmon";
52 io-channels = <&adc0 16>, <&adc1 16>;
53 };
54
55 soc {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 compatible = "simple-bus";
59 interrupt-parent = <&mscm_ir>;
60 ranges;
61
62 aips0: bus@40000000 {
63 compatible = "fsl,aips-bus", "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <1>;
66 reg = <0x40000000 0x00070000>;
67 ranges;
68
69 mscm_cpucfg: cpucfg@40001000 {
70 compatible = "fsl,vf610-mscm-cpucfg", "syscon";
71 reg = <0x40001000 0x800>;
72 };
73
74 mscm_ir: interrupt-controller@40001800 {
75 compatible = "fsl,vf610-mscm-ir";
76 reg = <0x40001800 0x400>;
77 fsl,cpucfg = <&mscm_cpucfg>;
78 interrupt-controller;
79 #interrupt-cells = <2>;
80 };
81
82 edma0: dma-controller@40018000 {
83 #dma-cells = <2>;
84 compatible = "fsl,vf610-edma";
85 reg = <0x40018000 0x2000>,
86 <0x40024000 0x1000>,
87 <0x40025000 0x1000>;
88 dma-channels = <32>;
89 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
90 <9 IRQ_TYPE_LEVEL_HIGH>;
91 interrupt-names = "edma-tx", "edma-err";
92 clock-names = "dmamux0", "dmamux1";
93 clocks = <&clks VF610_CLK_DMAMUX0>,
94 <&clks VF610_CLK_DMAMUX1>;
95 status = "disabled";
96 };
97
98 can0: can@40020000 {
99 compatible = "fsl,vf610-flexcan";
100 reg = <0x40020000 0x4000>;
101 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&clks VF610_CLK_FLEXCAN0>,
103 <&clks VF610_CLK_FLEXCAN0>;
104 clock-names = "ipg", "per";
105 status = "disabled";
106 };
107
108 uart0: serial@40027000 {
109 compatible = "fsl,vf610-lpuart";
110 reg = <0x40027000 0x1000>;
111 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_UART0>;
113 clock-names = "ipg";
114 dmas = <&edma0 0 2>, <&edma0 0 3>;
115 dma-names = "rx","tx";
116 status = "disabled";
117 };
118
119 uart1: serial@40028000 {
120 compatible = "fsl,vf610-lpuart";
121 reg = <0x40028000 0x1000>;
122 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&clks VF610_CLK_UART1>;
124 clock-names = "ipg";
125 dmas = <&edma0 0 4>, <&edma0 0 5>;
126 dma-names = "rx","tx";
127 status = "disabled";
128 };
129
130 uart2: serial@40029000 {
131 compatible = "fsl,vf610-lpuart";
132 reg = <0x40029000 0x1000>;
133 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clks VF610_CLK_UART2>;
135 clock-names = "ipg";
136 dmas = <&edma0 0 6>, <&edma0 0 7>;
137 dma-names = "rx","tx";
138 status = "disabled";
139 };
140
141 uart3: serial@4002a000 {
142 compatible = "fsl,vf610-lpuart";
143 reg = <0x4002a000 0x1000>;
144 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&clks VF610_CLK_UART3>;
146 clock-names = "ipg";
147 dmas = <&edma0 0 8>, <&edma0 0 9>;
148 dma-names = "rx","tx";
149 status = "disabled";
150 };
151
152 dspi0: spi@4002c000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,vf610-dspi";
156 reg = <0x4002c000 0x1000>;
157 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clks VF610_CLK_DSPI0>;
159 clock-names = "dspi";
160 spi-num-chipselects = <6>;
161 dmas = <&edma1 1 12>, <&edma1 1 13>;
162 dma-names = "rx", "tx";
163 status = "disabled";
164 };
165
166 dspi1: spi@4002d000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,vf610-dspi";
170 reg = <0x4002d000 0x1000>;
171 interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&clks VF610_CLK_DSPI1>;
173 clock-names = "dspi";
174 spi-num-chipselects = <4>;
175 dmas = <&edma1 1 14>, <&edma1 1 15>;
176 dma-names = "rx", "tx";
177 status = "disabled";
178 };
179
180 sai0: sai@4002f000 {
181 compatible = "fsl,vf610-sai";
182 reg = <0x4002f000 0x1000>;
183 interrupts = <84 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clks VF610_CLK_SAI0>,
185 <&clks VF610_CLK_SAI0_DIV>,
186 <&clks 0>, <&clks 0>;
187 clock-names = "bus", "mclk1", "mclk2", "mclk3";
188 dma-names = "rx", "tx";
189 dmas = <&edma0 0 16>, <&edma0 0 17>;
190 status = "disabled";
191 };
192
193 sai1: sai@40030000 {
194 compatible = "fsl,vf610-sai";
195 reg = <0x40030000 0x1000>;
196 interrupts = <85 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clks VF610_CLK_SAI1>,
198 <&clks VF610_CLK_SAI1_DIV>,
199 <&clks 0>, <&clks 0>;
200 clock-names = "bus", "mclk1", "mclk2", "mclk3";
201 dma-names = "rx", "tx";
202 dmas = <&edma0 0 18>, <&edma0 0 19>;
203 status = "disabled";
204 };
205
206 sai2: sai@40031000 {
207 compatible = "fsl,vf610-sai";
208 reg = <0x40031000 0x1000>;
209 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clks VF610_CLK_SAI2>,
211 <&clks VF610_CLK_SAI2_DIV>,
212 <&clks 0>, <&clks 0>;
213 clock-names = "bus", "mclk1", "mclk2", "mclk3";
214 dma-names = "rx", "tx";
215 dmas = <&edma0 0 20>, <&edma0 0 21>;
216 status = "disabled";
217 };
218
219 sai3: sai@40032000 {
220 compatible = "fsl,vf610-sai";
221 reg = <0x40032000 0x1000>;
222 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clks VF610_CLK_SAI3>,
224 <&clks VF610_CLK_SAI3_DIV>,
225 <&clks 0>, <&clks 0>;
226 clock-names = "bus", "mclk1", "mclk2", "mclk3";
227 dma-names = "rx", "tx";
228 dmas = <&edma0 1 8>, <&edma0 1 9>;
229 status = "disabled";
230 };
231
232 pit: pit@40037000 {
233 compatible = "fsl,vf610-pit";
234 reg = <0x40037000 0x1000>;
235 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clks VF610_CLK_PIT>;
237 clock-names = "pit";
238 };
239
240 pwm0: pwm@40038000 {
241 compatible = "fsl,vf610-ftm-pwm";
242 #pwm-cells = <3>;
243 reg = <0x40038000 0x1000>;
244 clock-names = "ftm_sys", "ftm_ext",
245 "ftm_fix", "ftm_cnt_clk_en";
246 clocks = <&clks VF610_CLK_FTM0>,
247 <&clks VF610_CLK_FTM0_EXT_SEL>,
248 <&clks VF610_CLK_FTM0_FIX_SEL>,
249 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
250 status = "disabled";
251 };
252
253 pwm1: pwm@40039000 {
254 compatible = "fsl,vf610-ftm-pwm";
255 #pwm-cells = <3>;
256 reg = <0x40039000 0x1000>;
257 clock-names = "ftm_sys", "ftm_ext",
258 "ftm_fix", "ftm_cnt_clk_en";
259 clocks = <&clks VF610_CLK_FTM1>,
260 <&clks VF610_CLK_FTM1_EXT_SEL>,
261 <&clks VF610_CLK_FTM1_FIX_SEL>,
262 <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
263 status = "disabled";
264 };
265
266 adc0: adc@4003b000 {
267 compatible = "fsl,vf610-adc";
268 reg = <0x4003b000 0x1000>;
269 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clks VF610_CLK_ADC0>;
271 clock-names = "adc";
272 #io-channel-cells = <1>;
273 status = "disabled";
274 fsl,adck-max-frequency = <30000000>, <40000000>,
275 <20000000>;
276 };
277
278 tcon0: timing-controller@4003d000 {
279 compatible = "fsl,vf610-tcon";
280 reg = <0x4003d000 0x1000>;
281 clocks = <&clks VF610_CLK_TCON0>;
282 clock-names = "ipg";
283 status = "disabled";
284 };
285
286 wdoga5: watchdog@4003e000 {
287 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
288 reg = <0x4003e000 0x1000>;
289 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks VF610_CLK_WDT>;
291 status = "disabled";
292 };
293
294 qspi0: spi@40044000 {
295 #address-cells = <1>;
296 #size-cells = <0>;
297 compatible = "fsl,vf610-qspi";
298 reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
299 reg-names = "QuadSPI", "QuadSPI-memory";
300 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clks VF610_CLK_QSPI0_EN>,
302 <&clks VF610_CLK_QSPI0>;
303 clock-names = "qspi_en", "qspi";
304 status = "disabled";
305 };
306
307 iomuxc: iomuxc@40048000 {
308 compatible = "fsl,vf610-iomuxc";
309 reg = <0x40048000 0x1000>;
310 };
311
312 gpio0: gpio@40049000 {
313 compatible = "fsl,vf610-gpio";
314 reg = <0x40049000 0x1000 0x400ff000 0x40>;
315 gpio-controller;
316 #gpio-cells = <2>;
317 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 gpio-ranges = <&iomuxc 0 0 32>;
321 };
322
323 gpio1: gpio@4004a000 {
324 compatible = "fsl,vf610-gpio";
325 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 gpio-ranges = <&iomuxc 0 32 32>;
332 };
333
334 gpio2: gpio@4004b000 {
335 compatible = "fsl,vf610-gpio";
336 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
337 gpio-controller;
338 #gpio-cells = <2>;
339 interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 gpio-ranges = <&iomuxc 0 64 32>;
343 };
344
345 gpio3: gpio@4004c000 {
346 compatible = "fsl,vf610-gpio";
347 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 gpio-ranges = <&iomuxc 0 96 32>;
354 };
355
356 gpio4: gpio@4004d000 {
357 compatible = "fsl,vf610-gpio";
358 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
359 gpio-controller;
360 #gpio-cells = <2>;
361 interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 gpio-ranges = <&iomuxc 0 128 7>;
365 };
366
367 anatop: anatop@40050000 {
368 compatible = "fsl,vf610-anatop", "syscon";
369 reg = <0x40050000 0x400>;
370 };
371
372 usbphy0: usbphy@40050800 {
373 compatible = "fsl,vf610-usbphy";
374 reg = <0x40050800 0x400>;
375 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clks VF610_CLK_USBPHY0>;
377 fsl,anatop = <&anatop>;
378 status = "disabled";
379 };
380
381 usbphy1: usbphy@40050c00 {
382 compatible = "fsl,vf610-usbphy";
383 reg = <0x40050c00 0x400>;
384 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clks VF610_CLK_USBPHY1>;
386 fsl,anatop = <&anatop>;
387 status = "disabled";
388 };
389
390 dcu0: dcu@40058000 {
391 compatible = "fsl,vf610-dcu";
392 reg = <0x40058000 0x1200>;
393 interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks VF610_CLK_DCU0>,
395 <&clks VF610_CLK_DCU0_DIV>;
396 clock-names = "dcu", "pix";
397 fsl,tcon = <&tcon0>;
398 status = "disabled";
399 };
400
401 i2c0: i2c@40066000 {
402 #address-cells = <1>;
403 #size-cells = <0>;
404 compatible = "fsl,vf610-i2c";
405 reg = <0x40066000 0x1000>;
406 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clks VF610_CLK_I2C0>;
408 clock-names = "ipg";
409 dmas = <&edma0 0 50>,
410 <&edma0 0 51>;
411 dma-names = "rx","tx";
412 status = "disabled";
413 };
414
415 i2c1: i2c@40067000 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 compatible = "fsl,vf610-i2c";
419 reg = <0x40067000 0x1000>;
420 interrupts = <72 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&clks VF610_CLK_I2C1>;
422 clock-names = "ipg";
423 dmas = <&edma0 0 52>, <&edma0 0 53>;
424 dma-names = "rx","tx";
425 status = "disabled";
426 };
427
428 clks: ccm@4006b000 {
429 compatible = "fsl,vf610-ccm";
430 reg = <0x4006b000 0x1000>;
431 clocks = <&sxosc>, <&fxosc>;
432 clock-names = "sxosc", "fxosc";
433 #clock-cells = <1>;
434 };
435
436 usbdev0: usb@40034000 {
437 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
438 reg = <0x40034000 0x800>;
439 interrupts = <75 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks VF610_CLK_USBC0>;
441 fsl,usbphy = <&usbphy0>;
442 fsl,usbmisc = <&usbmisc0 0>;
443 dr_mode = "peripheral";
444 status = "disabled";
445 };
446
447 usbmisc0: usb@40034800 {
448 #index-cells = <1>;
449 compatible = "fsl,vf610-usbmisc";
450 reg = <0x40034800 0x200>;
451 clocks = <&clks VF610_CLK_USBC0>;
452 status = "disabled";
453 };
454
455 src: src@4006e000 {
456 compatible = "fsl,vf610-src", "syscon";
457 reg = <0x4006e000 0x1000>;
458 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>;
459 };
460 };
461
462 aips1: bus@40080000 {
463 compatible = "fsl,aips-bus", "simple-bus";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 reg = <0x40080000 0x0007f000>;
467 ranges;
468
469 edma1: dma-controller@40098000 {
470 #dma-cells = <2>;
471 compatible = "fsl,vf610-edma";
472 reg = <0x40098000 0x2000>,
473 <0x400a1000 0x1000>,
474 <0x400a2000 0x1000>;
475 dma-channels = <32>;
476 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
477 <11 IRQ_TYPE_LEVEL_HIGH>;
478 interrupt-names = "edma-tx", "edma-err";
479 clock-names = "dmamux0", "dmamux1";
480 clocks = <&clks VF610_CLK_DMAMUX2>,
481 <&clks VF610_CLK_DMAMUX3>;
482 status = "disabled";
483 };
484
485 ocotp: ocotp@400a5000 {
486 compatible = "fsl,vf610-ocotp", "syscon";
487 reg = <0x400a5000 0x1000>;
488 clocks = <&clks VF610_CLK_OCOTP>;
489 };
490
491 snvs0: snvs@400a7000 {
492 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
493 reg = <0x400a7000 0x2000>;
494
495 snvsrtc: snvs-rtc-lp {
496 compatible = "fsl,sec-v4.0-mon-rtc-lp";
497 regmap = <&snvs0>;
498 offset = <0x34>;
499 interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&clks VF610_CLK_SNVS>;
501 clock-names = "snvs-rtc";
502 };
503 };
504
505 uart4: serial@400a9000 {
506 compatible = "fsl,vf610-lpuart";
507 reg = <0x400a9000 0x1000>;
508 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clks VF610_CLK_UART4>;
510 clock-names = "ipg";
511 status = "disabled";
512 };
513
514 uart5: serial@400aa000 {
515 compatible = "fsl,vf610-lpuart";
516 reg = <0x400aa000 0x1000>;
517 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&clks VF610_CLK_UART5>;
519 clock-names = "ipg";
520 status = "disabled";
521 };
522
523 dspi2: spi@400ac000 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "fsl,vf610-dspi";
527 reg = <0x400ac000 0x1000>;
528 interrupts = <69 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&clks VF610_CLK_DSPI2>;
530 clock-names = "dspi";
531 spi-num-chipselects = <2>;
532 dmas = <&edma1 0 10>,
533 <&edma1 0 11>;
534 dma-names = "rx", "tx";
535 status = "disabled";
536 };
537
538 dspi3: spi@400ad000 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 compatible = "fsl,vf610-dspi";
542 reg = <0x400ad000 0x1000>;
543 interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clks VF610_CLK_DSPI3>;
545 clock-names = "dspi";
546 spi-num-chipselects = <2>;
547 dmas = <&edma1 0 12>, <&edma1 0 13>;
548 dma-names = "rx", "tx";
549 status = "disabled";
550 };
551
552 adc1: adc@400bb000 {
553 compatible = "fsl,vf610-adc";
554 reg = <0x400bb000 0x1000>;
555 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clks VF610_CLK_ADC1>;
557 clock-names = "adc";
558 #io-channel-cells = <1>;
559 status = "disabled";
560 fsl,adck-max-frequency = <30000000>, <40000000>,
561 <20000000>;
562 };
563
564 esdhc0: mmc@400b1000 {
565 compatible = "fsl,imx53-esdhc";
566 reg = <0x400b1000 0x1000>;
567 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&clks VF610_CLK_IPG_BUS>,
569 <&clks VF610_CLK_PLATFORM_BUS>,
570 <&clks VF610_CLK_ESDHC0>;
571 clock-names = "ipg", "ahb", "per";
572 status = "disabled";
573 };
574
575 esdhc1: mmc@400b2000 {
576 compatible = "fsl,imx53-esdhc";
577 reg = <0x400b2000 0x1000>;
578 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&clks VF610_CLK_IPG_BUS>,
580 <&clks VF610_CLK_PLATFORM_BUS>,
581 <&clks VF610_CLK_ESDHC1>;
582 clock-names = "ipg", "ahb", "per";
583 status = "disabled";
584 };
585
586 usbh1: usb@400b4000 {
587 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
588 reg = <0x400b4000 0x800>;
589 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clks VF610_CLK_USBC1>;
591 fsl,usbphy = <&usbphy1>;
592 fsl,usbmisc = <&usbmisc1 0>;
593 dr_mode = "host";
594 status = "disabled";
595 };
596
597 usbmisc1: usb@400b4800 {
598 #index-cells = <1>;
599 compatible = "fsl,vf610-usbmisc";
600 reg = <0x400b4800 0x200>;
601 clocks = <&clks VF610_CLK_USBC1>;
602 status = "disabled";
603 };
604
605 ftm: ftm@400b8000 {
606 compatible = "fsl,ftm-timer";
607 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
608 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
609 clock-names = "ftm-evt", "ftm-src",
610 "ftm-evt-counter-en", "ftm-src-counter-en";
611 clocks = <&clks VF610_CLK_FTM2>,
612 <&clks VF610_CLK_FTM3>,
613 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
614 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
615 status = "disabled";
616 };
617
618 qspi1: spi@400c4000 {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 compatible = "fsl,vf610-qspi";
622 reg = <0x400c4000 0x1000>, <0x50000000 0x10000000>;
623 reg-names = "QuadSPI", "QuadSPI-memory";
624 interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clks VF610_CLK_QSPI1_EN>,
626 <&clks VF610_CLK_QSPI1>;
627 clock-names = "qspi_en", "qspi";
628 status = "disabled";
629 };
630
631 dac0: dac@400cc000 {
632 compatible = "fsl,vf610-dac";
633 reg = <0x400cc000 1000>;
634 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
635 clock-names = "dac";
636 clocks = <&clks VF610_CLK_DAC0>;
637 status = "disabled";
638 };
639
640 dac1: dac@400cd000 {
641 compatible = "fsl,vf610-dac";
642 reg = <0x400cd000 1000>;
643 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
644 clock-names = "dac";
645 clocks = <&clks VF610_CLK_DAC1>;
646 status = "disabled";
647 };
648
649 fec0: ethernet@400d0000 {
650 compatible = "fsl,mvf600-fec";
651 reg = <0x400d0000 0x1000>;
652 interrupts = <78 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clks VF610_CLK_ENET0>,
654 <&clks VF610_CLK_ENET0>,
655 <&clks VF610_CLK_ENET>;
656 clock-names = "ipg", "ahb", "ptp";
657 status = "disabled";
658 };
659
660 fec1: ethernet@400d1000 {
661 compatible = "fsl,mvf600-fec";
662 reg = <0x400d1000 0x1000>;
663 interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&clks VF610_CLK_ENET1>,
665 <&clks VF610_CLK_ENET1>,
666 <&clks VF610_CLK_ENET>;
667 clock-names = "ipg", "ahb", "ptp";
668 status = "disabled";
669 };
670
671 can1: can@400d4000 {
672 compatible = "fsl,vf610-flexcan";
673 reg = <0x400d4000 0x4000>;
674 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&clks VF610_CLK_FLEXCAN1>,
676 <&clks VF610_CLK_FLEXCAN1>;
677 clock-names = "ipg", "per";
678 status = "disabled";
679 };
680
681 nfc: nand@400e0000 {
682 #address-cells = <1>;
683 #size-cells = <0>;
684 compatible = "fsl,vf610-nfc";
685 reg = <0x400e0000 0x4000>;
686 interrupts = <83 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&clks VF610_CLK_NFC>;
688 clock-names = "nfc";
689 status = "disabled";
690 };
691
692 i2c2: i2c@400e6000 {
693 #address-cells = <1>;
694 #size-cells = <0>;
695 compatible = "fsl,vf610-i2c";
696 reg = <0x400e6000 0x1000>;
697 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clks VF610_CLK_I2C2>;
699 clock-names = "ipg";
700 dmas = <&edma0 1 36>,
701 <&edma0 1 37>;
702 dma-names = "rx","tx";
703 status = "disabled";
704 };
705
706 i2c3: i2c@400e7000 {
707 #address-cells = <1>;
708 #size-cells = <0>;
709 compatible = "fsl,vf610-i2c";
710 reg = <0x400e7000 0x1000>;
711 interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clks VF610_CLK_I2C3>;
713 clock-names = "ipg";
714 dmas = <&edma0 1 38>, <&edma0 1 39>;
715 dma-names = "rx","tx";
716 status = "disabled";
717 };
718
719 crypto: crypto@400f0000 {
720 compatible = "fsl,sec-v4.0";
721 #address-cells = <1>;
722 #size-cells = <1>;
723 reg = <0x400f0000 0x9000>;
724 ranges = <0 0x400f0000 0x9000>;
725 clocks = <&clks VF610_CLK_CAAM>;
726 clock-names = "ipg";
727
728 sec_jr0: jr0@1000 {
729 compatible = "fsl,sec-v4.0-job-ring";
730 reg = <0x1000 0x1000>;
731 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
732 };
733
734 sec_jr1: jr1@2000 {
735 compatible = "fsl,sec-v4.0-job-ring";
736 reg = <0x2000 0x1000>;
737 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
738 };
739 };
740 };
741 };
742};