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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm / nxp / imx / imx6ul-tx6ul.dtsi
blob: 1db146ac1c176b9ebf31d7b6d8d944c6bd0d822b [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1/*
2 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/gpio/gpio.h>
43#include <dt-bindings/interrupt-controller/irq.h>
44#include <dt-bindings/pwm/pwm.h>
45
46/ {
47 aliases {
48 can0 = &can2;
49 can1 = &can1;
50 display = &display;
51 i2c0 = &i2c2;
52 i2c1 = &i2c_gpio;
53 i2c2 = &i2c1;
54 i2c3 = &i2c3;
55 i2c4 = &i2c4;
56 lcdif-23bit-pins-a = &pinctrl_disp0_1;
57 lcdif-24bit-pins-a = &pinctrl_disp0_2;
58 pwm0 = &pwm5;
59 reg-can-xcvr = &reg_can_xcvr;
60 serial2 = &uart5;
61 serial4 = &uart3;
62 spi0 = &ecspi2;
63 spi1 = &spi_gpio;
64 stk5led = &user_led;
65 usbh1 = &usbotg2;
66 usbotg = &usbotg1;
67 };
68
69 chosen {
70 stdout-path = &uart1;
71 };
72
73 memory@80000000 {
74 device_type = "memory";
75 reg = <0x80000000 0>; /* will be filled by U-Boot */
76 };
77
78 clocks {
79 mclk: mclk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <26000000>;
83 };
84 };
85
86 backlight: backlight {
87 compatible = "pwm-backlight";
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_lcd_rst>;
90 enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
91 pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>;
92 power-supply = <&reg_lcd_pwr>;
93 /*
94 * a poor man's way to create a 1:1 relationship between
95 * the PWM value and the actual duty cycle
96 */
97 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
98 10 11 12 13 14 15 16 17 18 19
99 20 21 22 23 24 25 26 27 28 29
100 30 31 32 33 34 35 36 37 38 39
101 40 41 42 43 44 45 46 47 48 49
102 50 51 52 53 54 55 56 57 58 59
103 60 61 62 63 64 65 66 67 68 69
104 70 71 72 73 74 75 76 77 78 79
105 80 81 82 83 84 85 86 87 88 89
106 90 91 92 93 94 95 96 97 98 99
107 100>;
108 default-brightness-level = <50>;
109 };
110
111 i2c_gpio: i2c-gpio {
112 compatible = "i2c-gpio";
113 #address-cells = <1>;
114 #size-cells = <0>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_i2c_gpio>;
117 sda-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
118 scl-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
119 clock-frequency = <400000>;
120 status = "okay";
121
122 ds1339: rtc@68 {
123 compatible = "dallas,ds1339";
124 reg = <0x68>;
125 status = "disabled";
126 };
127 };
128
129 leds {
130 compatible = "gpio-leds";
131
132 user_led: led-user {
133 label = "Heartbeat";
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_led>;
136 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
137 linux,default-trigger = "heartbeat";
138 };
139 };
140
141 reg_3v3_etn: regulator-3v3etn {
142 compatible = "regulator-fixed";
143 regulator-name = "3V3_ETN";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_etnphy_power>;
148 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
149 enable-active-high;
150 };
151
152 reg_2v5: regulator-2v5 {
153 compatible = "regulator-fixed";
154 regulator-name = "2V5";
155 regulator-min-microvolt = <2500000>;
156 regulator-max-microvolt = <2500000>;
157 regulator-always-on;
158 };
159
160 reg_3v3: regulator-3v3 {
161 compatible = "regulator-fixed";
162 regulator-name = "3V3";
163 regulator-min-microvolt = <3300000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-always-on;
166 };
167
168 reg_can_xcvr: regulator-canxcvr {
169 compatible = "regulator-fixed";
170 regulator-name = "CAN XCVR";
171 regulator-min-microvolt = <3300000>;
172 regulator-max-microvolt = <3300000>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
175 gpio = <&gpio3 5 GPIO_ACTIVE_LOW>;
176 };
177
178 reg_lcd_pwr: regulator-lcdpwr {
179 compatible = "regulator-fixed";
180 regulator-name = "LCD POWER";
181 regulator-min-microvolt = <3300000>;
182 regulator-max-microvolt = <3300000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_lcd_pwr>;
185 gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>;
186 enable-active-high;
187 regulator-boot-on;
188 regulator-always-on;
189 };
190
191 reg_usbh1_vbus: regulator-usbh1vbus {
192 compatible = "regulator-fixed";
193 regulator-name = "usbh1_vbus";
194 regulator-min-microvolt = <5000000>;
195 regulator-max-microvolt = <5000000>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>;
198 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
199 enable-active-high;
200 };
201
202 reg_usbotg_vbus: regulator-usbotgvbus {
203 compatible = "regulator-fixed";
204 regulator-name = "usbotg_vbus";
205 regulator-min-microvolt = <5000000>;
206 regulator-max-microvolt = <5000000>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>;
209 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
210 enable-active-high;
211 };
212
213 spi_gpio: spi {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "spi-gpio";
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_spi_gpio>;
219 mosi-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
220 miso-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
221 sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
222 num-chipselects = <2>;
223 cs-gpios = <
224 &gpio1 29 GPIO_ACTIVE_HIGH
225 &gpio1 10 GPIO_ACTIVE_HIGH
226 >;
227 status = "disabled";
228 };
229
230 sound {
231 compatible = "karo,imx6ul-tx6ul-sgtl5000",
232 "simple-audio-card";
233 simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio";
234 simple-audio-card,format = "i2s";
235 simple-audio-card,bitclock-master = <&codec_dai>;
236 simple-audio-card,frame-master = <&codec_dai>;
237 simple-audio-card,widgets =
238 "Microphone", "Mic Jack",
239 "Line", "Line In",
240 "Line", "Line Out",
241 "Headphone", "Headphone Jack";
242 simple-audio-card,routing =
243 "MIC_IN", "Mic Jack",
244 "Mic Jack", "Mic Bias",
245 "Headphone Jack", "HP_OUT";
246
247 cpu_dai: simple-audio-card,cpu {
248 sound-dai = <&sai2>;
249 };
250
251 codec_dai: simple-audio-card,codec {
252 sound-dai = <&sgtl5000>;
253 };
254 };
255};
256
257&can1 {
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_flexcan1>;
260 xceiver-supply = <&reg_can_xcvr>;
261 status = "okay";
262};
263
264&can2 {
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_flexcan2>;
267 xceiver-supply = <&reg_can_xcvr>;
268 status = "okay";
269};
270
271&ecspi2 {
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_ecspi2>;
274 cs-gpios = <
275 &gpio1 29 GPIO_ACTIVE_HIGH
276 &gpio1 10 GPIO_ACTIVE_HIGH
277 >;
278 status = "disabled";
279};
280
281&fec1 {
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
284 phy-mode = "rmii";
285 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
286 phy-supply = <&reg_3v3_etn>;
287 phy-handle = <&etnphy0>;
288 status = "okay";
289
290 mdio {
291 #address-cells = <1>;
292 #size-cells = <0>;
293
294 etnphy0: ethernet-phy@0 {
295 compatible = "ethernet-phy-ieee802.3-c22";
296 reg = <0>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_etnphy0_int>;
299 interrupt-parent = <&gpio5>;
300 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
301 status = "okay";
302 };
303
304 etnphy1: ethernet-phy@2 {
305 compatible = "ethernet-phy-ieee802.3-c22";
306 reg = <2>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_etnphy1_int>;
309 interrupt-parent = <&gpio4>;
310 interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
311 status = "okay";
312 };
313 };
314};
315
316&fec2 {
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
319 phy-mode = "rmii";
320 phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
321 phy-supply = <&reg_3v3_etn>;
322 phy-handle = <&etnphy1>;
323 status = "disabled";
324};
325
326&gpmi {
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_gpmi_nand>;
329 nand-on-flash-bbt;
330 fsl,no-blockmark-swap;
331 status = "okay";
332};
333
334&i2c2 {
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_i2c2>;
337 clock-frequency = <400000>;
338 status = "okay";
339
340 sgtl5000: codec@a {
341 compatible = "fsl,sgtl5000";
342 reg = <0x0a>;
343 #sound-dai-cells = <0>;
344 VDDA-supply = <&reg_2v5>;
345 VDDIO-supply = <&reg_3v3>;
346 clocks = <&mclk>;
347 };
348
349 polytouch: polytouch@38 {
350 compatible = "edt,edt-ft5x06";
351 reg = <0x38>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_edt_ft5x06>;
354 interrupt-parent = <&gpio5>;
355 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
356 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
357 wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
358 wakeup-source;
359 };
360
361 touchscreen: touchscreen@48 {
362 compatible = "ti,tsc2007";
363 reg = <0x48>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_tsc2007>;
366 interrupt-parent = <&gpio3>;
367 interrupts = <26 IRQ_TYPE_NONE>;
368 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
369 ti,x-plate-ohms = <660>;
370 wakeup-source;
371 };
372};
373
374&kpp {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_kpp>;
377 /* sample keymap */
378 /* row/col 0..3 are mapped to KPP row/col 4..7 */
379 linux,keymap = <
380 MATRIX_KEY(4, 4, KEY_POWER)
381 MATRIX_KEY(4, 5, KEY_KP0)
382 MATRIX_KEY(4, 6, KEY_KP1)
383 MATRIX_KEY(4, 7, KEY_KP2)
384 MATRIX_KEY(5, 4, KEY_KP3)
385 MATRIX_KEY(5, 5, KEY_KP4)
386 MATRIX_KEY(5, 6, KEY_KP5)
387 MATRIX_KEY(5, 7, KEY_KP6)
388 MATRIX_KEY(6, 4, KEY_KP7)
389 MATRIX_KEY(6, 5, KEY_KP8)
390 MATRIX_KEY(6, 6, KEY_KP9)
391 >;
392 status = "okay";
393};
394
395&lcdif {
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_disp0_1>;
398 lcd-supply = <&reg_lcd_pwr>;
399 display = <&display>;
400 status = "okay";
401
402 display: disp0 {
403 bits-per-pixel = <32>;
404 bus-width = <24>;
405 status = "okay";
406
407 display-timings {
408 VGA {
409 clock-frequency = <25200000>;
410 hactive = <640>;
411 vactive = <480>;
412 hback-porch = <48>;
413 hsync-len = <96>;
414 hfront-porch = <16>;
415 vback-porch = <31>;
416 vsync-len = <2>;
417 vfront-porch = <12>;
418 hsync-active = <0>;
419 vsync-active = <0>;
420 de-active = <1>;
421 pixelclk-active = <1>;
422 };
423
424 ETV570 {
425 clock-frequency = <25200000>;
426 hactive = <640>;
427 vactive = <480>;
428 hback-porch = <114>;
429 hsync-len = <30>;
430 hfront-porch = <16>;
431 vback-porch = <32>;
432 vsync-len = <3>;
433 vfront-porch = <10>;
434 hsync-active = <0>;
435 vsync-active = <0>;
436 de-active = <1>;
437 pixelclk-active = <1>;
438 };
439
440 ET0350 {
441 clock-frequency = <6413760>;
442 hactive = <320>;
443 vactive = <240>;
444 hback-porch = <34>;
445 hsync-len = <34>;
446 hfront-porch = <20>;
447 vback-porch = <15>;
448 vsync-len = <3>;
449 vfront-porch = <4>;
450 hsync-active = <0>;
451 vsync-active = <0>;
452 de-active = <1>;
453 pixelclk-active = <1>;
454 };
455
456 ET0430 {
457 clock-frequency = <9009000>;
458 hactive = <480>;
459 vactive = <272>;
460 hback-porch = <2>;
461 hsync-len = <41>;
462 hfront-porch = <2>;
463 vback-porch = <2>;
464 vsync-len = <10>;
465 vfront-porch = <2>;
466 hsync-active = <0>;
467 vsync-active = <0>;
468 de-active = <1>;
469 pixelclk-active = <0>;
470 };
471
472 ET0500 {
473 clock-frequency = <33264000>;
474 hactive = <800>;
475 vactive = <480>;
476 hback-porch = <88>;
477 hsync-len = <128>;
478 hfront-porch = <40>;
479 vback-porch = <33>;
480 vsync-len = <2>;
481 vfront-porch = <10>;
482 hsync-active = <0>;
483 vsync-active = <0>;
484 de-active = <1>;
485 pixelclk-active = <1>;
486 };
487
488 ET0700 { /* same as ET0500 */
489 clock-frequency = <33264000>;
490 hactive = <800>;
491 vactive = <480>;
492 hback-porch = <88>;
493 hsync-len = <128>;
494 hfront-porch = <40>;
495 vback-porch = <33>;
496 vsync-len = <2>;
497 vfront-porch = <10>;
498 hsync-active = <0>;
499 vsync-active = <0>;
500 de-active = <1>;
501 pixelclk-active = <1>;
502 };
503
504 ETQ570 {
505 clock-frequency = <6596040>;
506 hactive = <320>;
507 vactive = <240>;
508 hback-porch = <38>;
509 hsync-len = <30>;
510 hfront-porch = <30>;
511 vback-porch = <16>;
512 vsync-len = <3>;
513 vfront-porch = <4>;
514 hsync-active = <0>;
515 vsync-active = <0>;
516 de-active = <1>;
517 pixelclk-active = <1>;
518 };
519 };
520 };
521};
522
523&pwm5 {
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_pwm5>;
526 status = "okay";
527};
528
529&sai2 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_sai2>;
532 status = "okay";
533};
534
535&uart1 {
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
538 uart-has-rtscts;
539 status = "okay";
540};
541
542&uart2 {
543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
545 uart-has-rtscts;
546 status = "okay";
547};
548
549&uart5 {
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
552 uart-has-rtscts;
553 status = "okay";
554};
555
556&usbotg1 {
557 vbus-supply = <&reg_usbotg_vbus>;
558 dr_mode = "peripheral";
559 disable-over-current;
560 status = "okay";
561};
562
563&usbotg2 {
564 vbus-supply = <&reg_usbh1_vbus>;
565 dr_mode = "host";
566 disable-over-current;
567 status = "okay";
568};
569
570&usdhc1 {
571 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>;
573 bus-width = <4>;
574 no-1-8-v;
575 cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
576 fsl,wp-controller;
577 status = "okay";
578};
579
580&iomuxc {
581 pinctrl-names = "default";
582 pinctrl-0 = <&pinctrl_hog>;
583
584 pinctrl_hog: hoggrp {
585 };
586
587 pinctrl_led: ledgrp {
588 fsl,pins = <
589 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */
590 >;
591 };
592
593 pinctrl_disp0_1: disp0grp-1 {
594 fsl,pins = <
595 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
596 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
597 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
598 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
599 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */
600 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
601 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
602 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
603 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
604 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
605 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
606 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
607 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
608 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
609 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
610 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
611 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
612 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
613 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
614 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
615 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
616 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
617 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
618 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
619 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
620 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
621 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
622 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
623 >;
624 };
625
626 pinctrl_disp0_2: disp0grp-2 {
627 fsl,pins = <
628 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
629 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
630 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
631 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
632 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10
633 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
634 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
635 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
636 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
637 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
638 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
639 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
640 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10
641 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10
642 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10
643 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10
644 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10
645 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10
646 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10
647 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10
648 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10
649 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10
650 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10
651 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10
652 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10
653 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10
654 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10
655 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10
656 >;
657 };
658
659 pinctrl_ecspi2: ecspi2grp {
660 fsl,pins = <
661 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
662 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
663 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */
664 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */
665 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */
666 >;
667 };
668
669 pinctrl_edt_ft5x06: edt-ft5x06grp {
670 fsl,pins = <
671 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */
672 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */
673 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */
674 >;
675 };
676
677 pinctrl_enet1: enet1grp {
678 fsl,pins = <
679 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0
680 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0
681 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0
682 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0
683 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0
684 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0
685 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0
686 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1
687 >;
688 };
689
690 pinctrl_enet2: enet2grp {
691 fsl,pins = <
692 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0
693 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0
694 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0
695 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0
696 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0
697 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0
698 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0
699 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1
700 >;
701 };
702
703 pinctrl_enet1_mdio: enet1-mdiogrp {
704 fsl,pins = <
705 MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0
706 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
707 >;
708 };
709
710 pinctrl_etnphy_power: etnphy-pwrgrp {
711 fsl,pins = <
712 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */
713 >;
714 };
715
716 pinctrl_etnphy0_int: etnphy-intgrp-0 {
717 fsl,pins = <
718 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */
719 >;
720 };
721
722 pinctrl_etnphy0_rst: etnphy-rstgrp-0 {
723 fsl,pins = <
724 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */
725 >;
726 };
727
728 pinctrl_etnphy1_int: etnphy-intgrp-1 {
729 fsl,pins = <
730 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */
731 >;
732 };
733
734 pinctrl_etnphy1_rst: etnphy-rstgrp-1 {
735 fsl,pins = <
736 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */
737 >;
738 };
739
740 pinctrl_flexcan1: flexcan1grp {
741 fsl,pins = <
742 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
743 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
744 >;
745 };
746
747 pinctrl_flexcan2: flexcan2grp {
748 fsl,pins = <
749 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
750 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
751 >;
752 };
753
754 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
755 fsl,pins = <
756 MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */
757 >;
758 };
759
760 pinctrl_gpmi_nand: gpminandgrp {
761 fsl,pins = <
762 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
763 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
764 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
765 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
766 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
767 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
768 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
769 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
770 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
771 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
772 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
773 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
774 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
775 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
776 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
777 >;
778 };
779
780 pinctrl_i2c_gpio: i2c-gpiogrp {
781 fsl,pins = <
782 MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */
783 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */
784 >;
785 };
786
787 pinctrl_i2c2: i2c2grp {
788 fsl,pins = <
789 MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1
790 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1
791 >;
792 };
793
794 pinctrl_kpp: kppgrp {
795 fsl,pins = <
796 MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0
797 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0
798 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0
799 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0
800 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0
801 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0
802 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0
803 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0
804 >;
805 };
806
807 pinctrl_lcd_pwr: lcd-pwrgrp {
808 fsl,pins = <
809 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */
810 >;
811 };
812
813 pinctrl_lcd_rst: lcd-rstgrp {
814 fsl,pins = <
815 MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */
816 >;
817 };
818
819 pinctrl_pwm5: pwm5grp {
820 fsl,pins = <
821 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0
822 >;
823 };
824
825 pinctrl_sai2: sai2grp {
826 fsl,pins = <
827 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */
828 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */
829 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */
830 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */
831 >;
832 };
833
834 pinctrl_spi_gpio: spi-gpiogrp {
835 fsl,pins = <
836 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */
837 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */
838 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */
839 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */
840 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */
841 >;
842 };
843
844 pinctrl_tsc2007: tsc2007grp {
845 fsl,pins = <
846 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */
847 >;
848 };
849
850 pinctrl_uart1: uart1grp {
851 fsl,pins = <
852 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0
853 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0
854 >;
855 };
856
857 pinctrl_uart1_rtscts: uart1-rtsctsgrp {
858 fsl,pins = <
859 MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0
860 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0
861 >;
862 };
863
864 pinctrl_uart2: uart2grp {
865 fsl,pins = <
866 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0
867 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0
868 >;
869 };
870
871 pinctrl_uart2_rtscts: uart2-rtsctsgrp {
872 fsl,pins = <
873 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0
874 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0
875 >;
876 };
877
878 pinctrl_uart5: uart5grp {
879 fsl,pins = <
880 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0
881 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0
882 >;
883 };
884
885 pinctrl_uart5_rtscts: uart5-rtsctsgrp {
886 fsl,pins = <
887 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0
888 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0
889 >;
890 };
891
892 pinctrl_usbh1_oc: usbh1-ocgrp {
893 fsl,pins = <
894 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */
895 >;
896 };
897
898 pinctrl_usbh1_vbus: usbh1-vbusgrp {
899 fsl,pins = <
900 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */
901 >;
902 };
903
904 pinctrl_usbotg_oc: usbotg-ocgrp {
905 fsl,pins = <
906 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */
907 >;
908 };
909
910 pinctrl_usbotg_vbus: usbotg-vbusgrp {
911 fsl,pins = <
912 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */
913 >;
914 };
915
916 pinctrl_usdhc1: usdhc1grp {
917 fsl,pins = <
918 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1
919 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099
920 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1
921 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1
922 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1
923 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1
924 >;
925 };
926
927 pinctrl_usdhc1_cd: usdhc1cdgrp {
928 fsl,pins = <
929 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */
930 >;
931 };
932
933 pinctrl_usdhc2: usdhc2grp {
934 fsl,pins = <
935 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1
936 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1
937 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1
938 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1
939 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1
940 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1
941 /* eMMC RESET */
942 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0
943 >;
944 };
945};