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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / src / arm / nxp / imx / imx6qdl-gw5907.dtsi
blob: 955a51226eda7566e17bdb891bf964badea8000d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 nand = &gpmi;
16 usb0 = &usbh1;
17 usb1 = &usbotg;
18 };
19
20 chosen {
21 stdout-path = &uart2;
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26
27 user-pb {
28 label = "user_pb";
29 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
30 linux,code = <BTN_0>;
31 };
32
33 user-pb1x {
34 label = "user_pb1x";
35 linux,code = <BTN_1>;
36 interrupt-parent = <&gsc>;
37 interrupts = <0>;
38 };
39
40 key-erased {
41 label = "key-erased";
42 linux,code = <BTN_2>;
43 interrupt-parent = <&gsc>;
44 interrupts = <1>;
45 };
46
47 eeprom-wp {
48 label = "eeprom_wp";
49 linux,code = <BTN_3>;
50 interrupt-parent = <&gsc>;
51 interrupts = <2>;
52 };
53
54 tamper {
55 label = "tamper";
56 linux,code = <BTN_4>;
57 interrupt-parent = <&gsc>;
58 interrupts = <5>;
59 };
60
61 switch-hold {
62 label = "switch_hold";
63 linux,code = <BTN_5>;
64 interrupt-parent = <&gsc>;
65 interrupts = <7>;
66 };
67 };
68
69 leds {
70 compatible = "gpio-leds";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_gpio_leds>;
73
74 led0: led-user1 {
75 label = "user1";
76 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
77 default-state = "on";
78 linux,default-trigger = "heartbeat";
79 };
80
81 led1: led-user2 {
82 label = "user2";
83 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
84 default-state = "off";
85 };
86 };
87
88 memory@10000000 {
89 device_type = "memory";
90 reg = <0x10000000 0x20000000>;
91 };
92
93 pps {
94 compatible = "pps-gpio";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pps>;
97 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
98 status = "okay";
99 };
100
101 reg_3p3v: regulator-3p3v {
102 compatible = "regulator-fixed";
103 regulator-name = "3P3V";
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 regulator-always-on;
107 };
108
109 reg_5p0v: regulator-5p0v {
110 compatible = "regulator-fixed";
111 regulator-name = "5P0V";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 regulator-always-on;
115 };
116
117 reg_usb_otg_vbus: regulator-usb-otg-vbus {
118 compatible = "regulator-fixed";
119 regulator-name = "usb_otg_vbus";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
123 enable-active-high;
124 };
125};
126
127&fec {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_enet>;
130 phy-mode = "rgmii-id";
131 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
132 status = "okay";
133};
134
135&gpmi {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_gpmi_nand>;
138 status = "okay";
139};
140
141&hdmi {
142 ddc-i2c-bus = <&i2c3>;
143 status = "okay";
144};
145
146&i2c1 {
147 clock-frequency = <100000>;
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_i2c1>;
150 status = "okay";
151
152 gsc: gsc@20 {
153 compatible = "gw,gsc";
154 reg = <0x20>;
155 interrupt-parent = <&gpio1>;
156 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
157 interrupt-controller;
158 #interrupt-cells = <1>;
159 #size-cells = <0>;
160
161 adc {
162 compatible = "gw,gsc-adc";
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 channel@0 {
167 gw,mode = <0>;
168 reg = <0x00>;
169 label = "temp";
170 };
171
172 channel@2 {
173 gw,mode = <1>;
174 reg = <0x02>;
175 label = "vdd_vin";
176 };
177
178 channel@5 {
179 gw,mode = <1>;
180 reg = <0x05>;
181 label = "vdd_3p3";
182 };
183
184 channel@8 {
185 gw,mode = <1>;
186 reg = <0x08>;
187 label = "vdd_bat";
188 };
189
190 channel@b {
191 gw,mode = <1>;
192 reg = <0x0b>;
193 label = "vdd_5p0";
194 };
195
196 channel@e {
197 gw,mode = <1>;
198 reg = <0xe>;
199 label = "vdd_arm";
200 };
201
202 channel@11 {
203 gw,mode = <1>;
204 reg = <0x11>;
205 label = "vdd_soc";
206 };
207
208 channel@14 {
209 gw,mode = <1>;
210 reg = <0x14>;
211 label = "vdd_3p0";
212 };
213
214 channel@17 {
215 gw,mode = <1>;
216 reg = <0x17>;
217 label = "vdd_1p5";
218 };
219
220 channel@1d {
221 gw,mode = <1>;
222 reg = <0x1d>;
223 label = "vdd_1p8";
224 };
225
226 channel@20 {
227 gw,mode = <1>;
228 reg = <0x20>;
229 label = "vdd_an1";
230 };
231
232 channel@23 {
233 gw,mode = <1>;
234 reg = <0x23>;
235 label = "vdd_2p5";
236 };
237 };
238 };
239
240 gsc_gpio: gpio@23 {
241 compatible = "nxp,pca9555";
242 reg = <0x23>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 interrupt-parent = <&gsc>;
246 interrupts = <4>;
247 };
248
249 eeprom@50 {
250 compatible = "atmel,24c02";
251 reg = <0x50>;
252 pagesize = <16>;
253 };
254
255 eeprom@51 {
256 compatible = "atmel,24c02";
257 reg = <0x51>;
258 pagesize = <16>;
259 };
260
261 eeprom@52 {
262 compatible = "atmel,24c02";
263 reg = <0x52>;
264 pagesize = <16>;
265 };
266
267 eeprom@53 {
268 compatible = "atmel,24c02";
269 reg = <0x53>;
270 pagesize = <16>;
271 };
272
273 ds1672@68 {
274 compatible = "dallas,ds1672";
275 reg = <0x68>;
276 };
277};
278
279&i2c2 {
280 clock-frequency = <100000>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_i2c2>;
283 status = "okay";
284};
285
286&i2c3 {
287 clock-frequency = <100000>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
290 status = "okay";
291
292 gpio@20 {
293 compatible = "nxp,pca9555";
294 reg = <0x20>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 };
298
299 adc@48 {
300 compatible = "ti,ads1015";
301 reg = <0x48>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304
305 channel@4 {
306 reg = <4>;
307 ti,gain = <0>;
308 ti,datarate = <5>;
309 };
310
311 channel@5 {
312 reg = <5>;
313 ti,gain = <0>;
314 ti,datarate = <5>;
315 };
316
317 channel@6 {
318 reg = <6>;
319 ti,gain = <0>;
320 ti,datarate = <5>;
321 };
322 };
323};
324
325&pcie {
326 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_pcie>;
328 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
329 status = "okay";
330};
331
332&pwm2 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
335 status = "disabled";
336};
337
338&pwm3 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
341 status = "disabled";
342};
343
344&pwm4 {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
347 status = "disabled";
348};
349
350&uart1 {
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_uart1>;
353 status = "okay";
354};
355
356&uart2 {
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_uart2>;
359 status = "okay";
360};
361
362&uart3 {
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_uart3>;
365 status = "okay";
366};
367
368&uart5 {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_uart5>;
371 status = "okay";
372};
373
374&usbotg {
375 vbus-supply = <&reg_usb_otg_vbus>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_usbotg>;
378 disable-over-current;
379 status = "okay";
380};
381
382&usbh1 {
383 status = "okay";
384};
385
386&wdog1 {
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_wdog>;
389 fsl,ext-reset-output;
390};
391
392&iomuxc {
393 pinctrl_enet: enetgrp {
394 fsl,pins = <
395 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
396 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
397 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
398 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
399 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
400 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
401 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
402 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
403 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
404 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
405 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
406 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
407 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
408 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
409 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
410 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
411 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
412 >;
413 };
414
415 pinctrl_gpio_leds: gpioledsgrp {
416 fsl,pins = <
417 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
418 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
419 >;
420 };
421
422 pinctrl_gpmi_nand: gpminandgrp {
423 fsl,pins = <
424 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
425 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
426 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
427 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
428 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
429 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
430 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
431 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
432 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
433 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
434 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
435 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
436 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
437 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
438 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
439 >;
440 };
441
442 pinctrl_i2c1: i2c1grp {
443 fsl,pins = <
444 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
445 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
446 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
447 >;
448 };
449
450 pinctrl_i2c2: i2c2grp {
451 fsl,pins = <
452 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
453 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
454 >;
455 };
456
457 pinctrl_i2c3: i2c3grp {
458 fsl,pins = <
459 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
460 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
461 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
462 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
463 >;
464 };
465
466 pinctrl_pcie: pciegrp {
467 fsl,pins = <
468 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
469 >;
470 };
471
472 pinctrl_pps: ppsgrp {
473 fsl,pins = <
474 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
475 >;
476 };
477
478 pinctrl_pwm2: pwm2grp {
479 fsl,pins = <
480 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
481 >;
482 };
483
484 pinctrl_pwm3: pwm3grp {
485 fsl,pins = <
486 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
487 >;
488 };
489
490 pinctrl_pwm4: pwm4grp {
491 fsl,pins = <
492 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
493 >;
494 };
495
496 pinctrl_uart1: uart1grp {
497 fsl,pins = <
498 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
499 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
500 >;
501 };
502
503 pinctrl_uart2: uart2grp {
504 fsl,pins = <
505 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
506 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
507 >;
508 };
509
510 pinctrl_uart3: uart3grp {
511 fsl,pins = <
512 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
513 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
514 >;
515 };
516
517 pinctrl_uart5: uart5grp {
518 fsl,pins = <
519 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
520 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
521 >;
522 };
523
524 pinctrl_usbotg: usbotggrp {
525 fsl,pins = <
526 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
527 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
528 >;
529 };
530
531 pinctrl_wdog: wdoggrp {
532 fsl,pins = <
533 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
534 >;
535 };
536};