| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | // |
| 3 | // Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de> |
| 4 | |
| 5 | /dts-v1/; |
| 6 | #include "imx6q.dtsi" |
| 7 | #include "imx6qdl-skov-cpu.dtsi" |
| 8 | #include "imx6qdl-skov-cpu-revc.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "SKOV IMX6 CPU QuadCore"; |
| 12 | compatible = "skov,imx6q-skov-revc-lt6", "fsl,imx6q"; |
| 13 | |
| 14 | backlight: backlight { |
| 15 | compatible = "pwm-backlight"; |
| 16 | pinctrl-names = "default"; |
| 17 | pinctrl-0 = <&pinctrl_backlight>; |
| 18 | enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; |
| 19 | pwms = <&pwm2 0 20000 0>; |
| 20 | brightness-levels = <0 255>; |
| 21 | num-interpolated-steps = <17>; |
| 22 | default-brightness-level = <8>; |
| 23 | power-supply = <®_24v0>; |
| 24 | }; |
| 25 | |
| 26 | display { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
| 29 | |
| 30 | compatible = "fsl,imx-parallel-display"; |
| 31 | pinctrl-names = "default"; |
| 32 | pinctrl-0 = <&pinctrl_ipu1>; |
| 33 | |
| 34 | port@0 { |
| 35 | reg = <0>; |
| 36 | |
| 37 | display0_in: endpoint { |
| 38 | remote-endpoint = <&ipu1_di0_disp0>; |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | port@1 { |
| 43 | reg = <1>; |
| 44 | |
| 45 | display0_out: endpoint { |
| 46 | remote-endpoint = <&panel_in>; |
| 47 | }; |
| 48 | }; |
| 49 | }; |
| 50 | |
| 51 | panel { |
| 52 | compatible = "logictechno,lttd800480070-l6wh-rt"; |
| 53 | backlight = <&backlight>; |
| 54 | power-supply = <®_3v3>; |
| 55 | |
| 56 | port { |
| 57 | panel_in: endpoint { |
| 58 | remote-endpoint = <&display0_out>; |
| 59 | }; |
| 60 | }; |
| 61 | }; |
| 62 | }; |
| 63 | |
| 64 | &hdmi { |
| 65 | ddc-i2c-bus = <&i2c2>; |
| 66 | status = "okay"; |
| 67 | }; |
| 68 | |
| 69 | &i2c2 { |
| 70 | pinctrl-names = "default"; |
| 71 | pinctrl-0 = <&pinctrl_i2c2>; |
| 72 | clock-frequency = <100000>; |
| 73 | status = "okay"; |
| 74 | }; |
| 75 | |
| 76 | &ipu1_di0_disp0 { |
| 77 | remote-endpoint = <&display0_in>; |
| 78 | }; |
| 79 | |
| 80 | &iomuxc { |
| 81 | pinctrl_backlight: backlightgrp { |
| 82 | fsl,pins = < |
| 83 | MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 |
| 84 | >; |
| 85 | }; |
| 86 | |
| 87 | pinctrl_i2c2: i2c2grp { |
| 88 | fsl,pins = < |
| 89 | /* internal 22 k pull up required */ |
| 90 | MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001F878 |
| 91 | /* internal 22 k pull up required */ |
| 92 | MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001F878 |
| 93 | >; |
| 94 | }; |
| 95 | |
| 96 | pinctrl_ipu1: ipu1grp { |
| 97 | fsl,pins = < |
| 98 | MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 |
| 99 | MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 |
| 100 | MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 |
| 101 | MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 |
| 102 | MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 |
| 103 | MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 |
| 104 | MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 |
| 105 | MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 |
| 106 | MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 |
| 107 | MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 |
| 108 | MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 |
| 109 | MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 |
| 110 | MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 |
| 111 | MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 |
| 112 | MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 |
| 113 | MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 |
| 114 | MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 |
| 115 | MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 |
| 116 | MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 |
| 117 | MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 |
| 118 | MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 |
| 119 | MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 |
| 120 | MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 |
| 121 | MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 |
| 122 | MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 |
| 123 | MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 |
| 124 | MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 |
| 125 | MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 |
| 126 | >; |
| 127 | }; |
| 128 | }; |