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Tom Rini53633a82024-02-29 12:33:36 -05001/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Linaro Limited
5 */
6
7#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H
8#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6375_H
9
10/* Clocks */
11#define DISP_CC_PLL0 0
12#define DISP_CC_MDSS_AHB_CLK 1
13#define DISP_CC_MDSS_AHB_CLK_SRC 2
14#define DISP_CC_MDSS_BYTE0_CLK 3
15#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
16#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
17#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
18#define DISP_CC_MDSS_ESC0_CLK 7
19#define DISP_CC_MDSS_ESC0_CLK_SRC 8
20#define DISP_CC_MDSS_MDP_CLK 9
21#define DISP_CC_MDSS_MDP_CLK_SRC 10
22#define DISP_CC_MDSS_MDP_LUT_CLK 11
23#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12
24#define DISP_CC_MDSS_PCLK0_CLK 13
25#define DISP_CC_MDSS_PCLK0_CLK_SRC 14
26#define DISP_CC_MDSS_ROT_CLK 15
27#define DISP_CC_MDSS_ROT_CLK_SRC 16
28#define DISP_CC_MDSS_RSCC_AHB_CLK 17
29#define DISP_CC_MDSS_RSCC_VSYNC_CLK 18
30#define DISP_CC_MDSS_VSYNC_CLK 19
31#define DISP_CC_MDSS_VSYNC_CLK_SRC 20
32#define DISP_CC_SLEEP_CLK 21
33#define DISP_CC_XO_CLK 22
34
35/* Resets */
36#define DISP_CC_MDSS_CORE_BCR 0
37#define DISP_CC_MDSS_RSCC_BCR 1
38
39/* GDSCs */
40#define MDSS_GDSC 0
41
42#endif