| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: MediaTek SoCs Watchdog timer |
| 8 | |
| 9 | maintainers: |
| 10 | - Matthias Brugger <matthias.bgg@gmail.com> |
| 11 | |
| 12 | description: |
| 13 | The watchdog supports a pre-timeout interrupt that fires |
| 14 | timeout-sec/2 before the expiry. |
| 15 | |
| 16 | allOf: |
| 17 | - $ref: watchdog.yaml# |
| 18 | |
| 19 | properties: |
| 20 | compatible: |
| 21 | oneOf: |
| 22 | - enum: |
| 23 | - mediatek,mt2712-wdt |
| 24 | - mediatek,mt6589-wdt |
| 25 | - mediatek,mt6735-wdt |
| 26 | - mediatek,mt6795-wdt |
| 27 | - mediatek,mt7986-wdt |
| Tom Rini | 93743d2 | 2024-04-01 09:08:13 -0400 | [diff] [blame^] | 28 | - mediatek,mt7988-wdt |
| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 29 | - mediatek,mt8183-wdt |
| 30 | - mediatek,mt8186-wdt |
| 31 | - mediatek,mt8188-wdt |
| 32 | - mediatek,mt8192-wdt |
| 33 | - mediatek,mt8195-wdt |
| 34 | - items: |
| 35 | - enum: |
| 36 | - mediatek,mt2701-wdt |
| 37 | - mediatek,mt6582-wdt |
| 38 | - mediatek,mt6797-wdt |
| 39 | - mediatek,mt7622-wdt |
| 40 | - mediatek,mt7623-wdt |
| 41 | - mediatek,mt7629-wdt |
| 42 | - mediatek,mt8173-wdt |
| 43 | - mediatek,mt8365-wdt |
| 44 | - mediatek,mt8516-wdt |
| 45 | - const: mediatek,mt6589-wdt |
| 46 | |
| 47 | reg: |
| 48 | maxItems: 1 |
| 49 | |
| 50 | interrupts: |
| 51 | items: |
| 52 | - description: Watchdog pre-timeout (bark) interrupt |
| 53 | |
| 54 | mediatek,disable-extrst: |
| 55 | description: Disable sending output reset signal |
| 56 | type: boolean |
| 57 | |
| 58 | mediatek,reset-by-toprgu: |
| 59 | description: The Top Reset Generation Unit (TOPRGU) generates reset signals |
| 60 | and distributes them to each IP. If present, the watchdog timer will be |
| 61 | reset by TOPRGU once system resets. |
| 62 | type: boolean |
| 63 | |
| 64 | '#reset-cells': |
| 65 | const: 1 |
| 66 | |
| 67 | required: |
| 68 | - compatible |
| 69 | - reg |
| 70 | |
| 71 | unevaluatedProperties: false |
| 72 | |
| 73 | examples: |
| 74 | - | |
| 75 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 76 | |
| 77 | soc { |
| 78 | #address-cells = <2>; |
| 79 | #size-cells = <2>; |
| 80 | |
| 81 | watchdog: watchdog@10007000 { |
| 82 | compatible = "mediatek,mt8183-wdt"; |
| 83 | reg = <0 0x10007000 0 0x100>; |
| 84 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; |
| 85 | mediatek,disable-extrst; |
| 86 | timeout-sec = <10>; |
| 87 | #reset-cells = <1>; |
| 88 | }; |
| 89 | }; |