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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / Bindings / ufs / qcom,ufs.yaml
blob: 10c146424baa1edd24c3e316625c07a35816f7f6 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15 properties:
16 compatible:
17 contains:
18 const: qcom,ufshc
19 required:
20 - compatible
21
22properties:
23 compatible:
24 items:
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,sa8775p-ufshc
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]30 - qcom,sc7280-ufshc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]31 - qcom,sc8280xp-ufshc
32 - qcom,sdm845-ufshc
33 - qcom,sm6115-ufshc
34 - qcom,sm6350-ufshc
35 - qcom,sm8150-ufshc
36 - qcom,sm8250-ufshc
37 - qcom,sm8350-ufshc
38 - qcom,sm8450-ufshc
39 - qcom,sm8550-ufshc
40 - qcom,sm8650-ufshc
41 - const: qcom,ufshc
42 - const: jedec,ufs-2.0
43
44 clocks:
45 minItems: 8
46 maxItems: 11
47
48 clock-names:
49 minItems: 8
50 maxItems: 11
51
52 dma-coherent: true
53
54 interconnects:
55 minItems: 2
56 maxItems: 2
57
58 interconnect-names:
59 items:
60 - const: ufs-ddr
61 - const: cpu-ufs
62
63 iommus:
64 minItems: 1
65 maxItems: 2
66
67 phys:
68 maxItems: 1
69
70 phy-names:
71 items:
72 - const: ufsphy
73
74 power-domains:
75 maxItems: 1
76
77 qcom,ice:
78 $ref: /schemas/types.yaml#/definitions/phandle
79 description: phandle to the Inline Crypto Engine node
80
81 reg:
82 minItems: 1
83 maxItems: 2
84
85 reg-names:
86 items:
87 - const: std
88 - const: ice
89
90 required-opps:
91 maxItems: 1
92
93 resets:
94 maxItems: 1
95
96 '#reset-cells':
97 const: 1
98
99 reset-names:
100 items:
101 - const: rst
102
103 reset-gpios:
104 maxItems: 1
105 description:
106 GPIO connected to the RESET pin of the UFS memory device.
107
108required:
109 - compatible
110 - reg
111
112allOf:
113 - $ref: ufs-common.yaml
114
115 - if:
116 properties:
117 compatible:
118 contains:
119 enum:
120 - qcom,msm8998-ufshc
121 - qcom,sa8775p-ufshc
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame^]122 - qcom,sc7280-ufshc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]123 - qcom,sc8280xp-ufshc
124 - qcom,sm8250-ufshc
125 - qcom,sm8350-ufshc
126 - qcom,sm8450-ufshc
127 - qcom,sm8550-ufshc
128 - qcom,sm8650-ufshc
129 then:
130 properties:
131 clocks:
132 minItems: 8
133 maxItems: 8
134 clock-names:
135 items:
136 - const: core_clk
137 - const: bus_aggr_clk
138 - const: iface_clk
139 - const: core_clk_unipro
140 - const: ref_clk
141 - const: tx_lane0_sync_clk
142 - const: rx_lane0_sync_clk
143 - const: rx_lane1_sync_clk
144 reg:
145 minItems: 1
146 maxItems: 1
147 reg-names:
148 maxItems: 1
149
150 - if:
151 properties:
152 compatible:
153 contains:
154 enum:
155 - qcom,sdm845-ufshc
156 - qcom,sm6350-ufshc
157 - qcom,sm8150-ufshc
158 then:
159 properties:
160 clocks:
161 minItems: 9
162 maxItems: 9
163 clock-names:
164 items:
165 - const: core_clk
166 - const: bus_aggr_clk
167 - const: iface_clk
168 - const: core_clk_unipro
169 - const: ref_clk
170 - const: tx_lane0_sync_clk
171 - const: rx_lane0_sync_clk
172 - const: rx_lane1_sync_clk
173 - const: ice_core_clk
174 reg:
175 minItems: 2
176 maxItems: 2
177 reg-names:
178 minItems: 2
179 required:
180 - reg-names
181
182 - if:
183 properties:
184 compatible:
185 contains:
186 enum:
187 - qcom,msm8996-ufshc
188 then:
189 properties:
190 clocks:
191 minItems: 11
192 maxItems: 11
193 clock-names:
194 items:
195 - const: core_clk_src
196 - const: core_clk
197 - const: bus_clk
198 - const: bus_aggr_clk
199 - const: iface_clk
200 - const: core_clk_unipro_src
201 - const: core_clk_unipro
202 - const: core_clk_ice
203 - const: ref_clk
204 - const: tx_lane0_sync_clk
205 - const: rx_lane0_sync_clk
206 reg:
207 minItems: 1
208 maxItems: 1
209 reg-names:
210 maxItems: 1
211
212 - if:
213 properties:
214 compatible:
215 contains:
216 enum:
217 - qcom,sm6115-ufshc
218 then:
219 properties:
220 clocks:
221 minItems: 8
222 maxItems: 8
223 clock-names:
224 items:
225 - const: core_clk
226 - const: bus_aggr_clk
227 - const: iface_clk
228 - const: core_clk_unipro
229 - const: ref_clk
230 - const: tx_lane0_sync_clk
231 - const: rx_lane0_sync_clk
232 - const: ice_core_clk
233 reg:
234 minItems: 2
235 maxItems: 2
236 reg-names:
237 minItems: 2
238 required:
239 - reg-names
240
241 # TODO: define clock bindings for qcom,msm8994-ufshc
242
243 - if:
244 required:
245 - qcom,ice
246 then:
247 properties:
248 reg:
249 maxItems: 1
250 clocks:
251 minItems: 8
252 maxItems: 8
253 else:
254 properties:
255 reg:
256 minItems: 1
257 maxItems: 2
258 clocks:
259 minItems: 8
260 maxItems: 11
261
262unevaluatedProperties: false
263
264examples:
265 - |
266 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
267 #include <dt-bindings/clock/qcom,rpmh.h>
268 #include <dt-bindings/gpio/gpio.h>
269 #include <dt-bindings/interconnect/qcom,sm8450.h>
270 #include <dt-bindings/interrupt-controller/arm-gic.h>
271
272 soc {
273 #address-cells = <2>;
274 #size-cells = <2>;
275
276 ufs@1d84000 {
277 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
278 "jedec,ufs-2.0";
279 reg = <0 0x01d84000 0 0x3000>;
280 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
281 phys = <&ufs_mem_phy_lanes>;
282 phy-names = "ufsphy";
283 lanes-per-direction = <2>;
284 #reset-cells = <1>;
285 resets = <&gcc GCC_UFS_PHY_BCR>;
286 reset-names = "rst";
287 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
288
289 vcc-supply = <&vreg_l7b_2p5>;
290 vcc-max-microamp = <1100000>;
291 vccq-supply = <&vreg_l9b_1p2>;
292 vccq-max-microamp = <1200000>;
293
294 power-domains = <&gcc UFS_PHY_GDSC>;
295 iommus = <&apps_smmu 0xe0 0x0>;
296 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
297 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
298 interconnect-names = "ufs-ddr", "cpu-ufs";
299
300 clock-names = "core_clk",
301 "bus_aggr_clk",
302 "iface_clk",
303 "core_clk_unipro",
304 "ref_clk",
305 "tx_lane0_sync_clk",
306 "rx_lane0_sync_clk",
307 "rx_lane1_sync_clk";
308 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
309 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
310 <&gcc GCC_UFS_PHY_AHB_CLK>,
311 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
312 <&rpmhcc RPMH_CXO_CLK>,
313 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
314 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
315 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
316 freq-table-hz = <75000000 300000000>,
317 <0 0>,
318 <0 0>,
319 <75000000 300000000>,
320 <75000000 300000000>,
321 <0 0>,
322 <0 0>,
323 <0 0>;
324 qcom,ice = <&ice>;
325 };
326 };