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git01.mediatek.com / filogic / uboot / 93743d241c64bc1f7ecbf3262d1683176551e11f / . / Bindings / mfd / rockchip,rk806.yaml
blob: 3c2b06629b75ea94f90712470bf14ed7fc16d68d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mfd/rockchip,rk806.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RK806 Power Management Integrated Circuit
8
9maintainers:
10 - Sebastian Reichel <sebastian.reichel@collabora.com>
11
12description:
13 Rockchip RK806 series PMIC. This device consists of an spi or
14 i2c controlled MFD that includes multiple switchable regulators.
15
16properties:
17 compatible:
18 enum:
19 - rockchip,rk806
20
21 reg:
22 maxItems: 1
23
24 interrupts:
25 maxItems: 1
26
27 gpio-controller: true
28
29 '#gpio-cells':
30 const: 2
31
32 system-power-controller: true
33
34 vcc1-supply:
35 description:
36 The input supply for dcdc-reg1.
37
38 vcc2-supply:
39 description:
40 The input supply for dcdc-reg2.
41
42 vcc3-supply:
43 description:
44 The input supply for dcdc-reg3.
45
46 vcc4-supply:
47 description:
48 The input supply for dcdc-reg4.
49
50 vcc5-supply:
51 description:
52 The input supply for dcdc-reg5.
53
54 vcc6-supply:
55 description:
56 The input supply for dcdc-reg6.
57
58 vcc7-supply:
59 description:
60 The input supply for dcdc-reg7.
61
62 vcc8-supply:
63 description:
64 The input supply for dcdc-reg8.
65
66 vcc9-supply:
67 description:
68 The input supply for dcdc-reg9.
69
70 vcc10-supply:
71 description:
72 The input supply for dcdc-reg10.
73
74 vcc11-supply:
75 description:
76 The input supply for pldo-reg1, pldo-reg2 and pldo-reg3.
77
78 vcc12-supply:
79 description:
80 The input supply for pldo-reg4 and pldo-reg5.
81
82 vcc13-supply:
83 description:
84 The input supply for nldo-reg1, nldo-reg2 and nldo-reg3.
85
86 vcc14-supply:
87 description:
88 The input supply for nldo-reg4 and nldo-reg5.
89
90 vcca-supply:
91 description:
92 The input supply for pldo-reg6.
93
94 regulators:
95 type: object
96 additionalProperties: false
97 patternProperties:
98 "^(dcdc-reg([1-9]|10)|pldo-reg[1-6]|nldo-reg[1-5])$":
99 type: object
100 $ref: /schemas/regulator/regulator.yaml#
101 unevaluatedProperties: false
102
103patternProperties:
104 '-pins$':
105 type: object
106 additionalProperties: false
107 $ref: /schemas/pinctrl/pinmux-node.yaml
108
109 properties:
110 function:
111 enum: [pin_fun0, pin_fun1, pin_fun2, pin_fun3, pin_fun4, pin_fun5]
112
113 pins:
114 $ref: /schemas/types.yaml#/definitions/string
115 enum: [gpio_pwrctrl1, gpio_pwrctrl2, gpio_pwrctrl3]
116
117allOf:
118 - $ref: /schemas/spi/spi-peripheral-props.yaml
119
120required:
121 - compatible
122 - reg
123 - interrupts
124
125unevaluatedProperties: false
126
127examples:
128 - |
129 #include <dt-bindings/pinctrl/rockchip.h>
130 #include <dt-bindings/interrupt-controller/irq.h>
131 #include <dt-bindings/gpio/gpio.h>
132 spi {
133 #address-cells = <1>;
134 #size-cells = <0>;
135
136 pmic@0 {
137 compatible = "rockchip,rk806";
138 reg = <0x0>;
139
140 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
141
142 vcc1-supply = <&vcc5v0_sys>;
143 vcc2-supply = <&vcc5v0_sys>;
144 vcc3-supply = <&vcc5v0_sys>;
145 vcc4-supply = <&vcc5v0_sys>;
146 vcc5-supply = <&vcc5v0_sys>;
147 vcc6-supply = <&vcc5v0_sys>;
148 vcc7-supply = <&vcc5v0_sys>;
149 vcc8-supply = <&vcc5v0_sys>;
150 vcc9-supply = <&vcc5v0_sys>;
151 vcc10-supply = <&vcc5v0_sys>;
152 vcc11-supply = <&vcc_2v0_pldo_s3>;
153 vcc12-supply = <&vcc5v0_sys>;
154 vcc13-supply = <&vcc5v0_sys>;
155 vcc14-supply = <&vcc_1v1_nldo_s3>;
156 vcca-supply = <&vcc5v0_sys>;
157
158 regulators {
159 vdd_gpu_s0: dcdc-reg1 {
160 regulator-always-on;
161 regulator-boot-on;
162 regulator-min-microvolt = <550000>;
163 regulator-max-microvolt = <950000>;
164 regulator-ramp-delay = <12500>;
165 regulator-name = "vdd_gpu_s0";
166 regulator-state-mem {
167 regulator-off-in-suspend;
168 };
169 };
170
171 vdd_npu_s0: dcdc-reg2 {
172 regulator-always-on;
173 regulator-boot-on;
174 regulator-min-microvolt = <550000>;
175 regulator-max-microvolt = <950000>;
176 regulator-ramp-delay = <12500>;
177 regulator-name = "vdd_npu_s0";
178 regulator-state-mem {
179 regulator-off-in-suspend;
180 };
181 };
182
183 vdd_log_s0: dcdc-reg3 {
184 regulator-always-on;
185 regulator-boot-on;
186 regulator-min-microvolt = <750000>;
187 regulator-max-microvolt = <750000>;
188 regulator-ramp-delay = <12500>;
189 regulator-name = "vdd_log_s0";
190 regulator-state-mem {
191 regulator-on-in-suspend;
192 regulator-suspend-microvolt = <750000>;
193 };
194 };
195
196 vdd_vdenc_s0: dcdc-reg4 {
197 regulator-always-on;
198 regulator-boot-on;
199 regulator-min-microvolt = <550000>;
200 regulator-max-microvolt = <950000>;
201 regulator-ramp-delay = <12500>;
202 regulator-name = "vdd_vdenc_s0";
203 regulator-state-mem {
204 regulator-off-in-suspend;
205 };
206 };
207
208 vdd_gpu_mem_s0: dcdc-reg5 {
209 regulator-always-on;
210 regulator-boot-on;
211 regulator-min-microvolt = <675000>;
212 regulator-max-microvolt = <950000>;
213 regulator-ramp-delay = <12500>;
214 regulator-name = "vdd_gpu_mem_s0";
215 regulator-state-mem {
216 regulator-off-in-suspend;
217 };
218 };
219
220 vdd_npu_mem_s0: dcdc-reg6 {
221 regulator-always-on;
222 regulator-boot-on;
223 regulator-min-microvolt = <675000>;
224 regulator-max-microvolt = <950000>;
225 regulator-ramp-delay = <12500>;
226 regulator-name = "vdd_npu_mem_s0";
227 regulator-state-mem {
228 regulator-off-in-suspend;
229 };
230 };
231
232 vcc_2v0_pldo_s3: dcdc-reg7 {
233 regulator-always-on;
234 regulator-boot-on;
235 regulator-min-microvolt = <2000000>;
236 regulator-max-microvolt = <2000000>;
237 regulator-ramp-delay = <12500>;
238 regulator-name = "vdd_2v0_pldo_s3";
239 regulator-state-mem {
240 regulator-on-in-suspend;
241 regulator-suspend-microvolt = <2000000>;
242 };
243 };
244
245 vdd_vdenc_mem_s0: dcdc-reg8 {
246 regulator-always-on;
247 regulator-boot-on;
248 regulator-min-microvolt = <675000>;
249 regulator-max-microvolt = <950000>;
250 regulator-ramp-delay = <12500>;
251 regulator-name = "vdd_vdenc_mem_s0";
252 regulator-state-mem {
253 regulator-off-in-suspend;
254 };
255 };
256
257 vdd2_ddr_s3: dcdc-reg9 {
258 regulator-always-on;
259 regulator-boot-on;
260 regulator-name = "vdd2_ddr_s3";
261 regulator-state-mem {
262 regulator-on-in-suspend;
263 };
264 };
265
266 vcc_1v1_nldo_s3: dcdc-reg10 {
267 regulator-always-on;
268 regulator-boot-on;
269 regulator-min-microvolt = <1100000>;
270 regulator-max-microvolt = <1100000>;
271 regulator-ramp-delay = <12500>;
272 regulator-name = "vcc_1v1_nldo_s3";
273 regulator-state-mem {
274 regulator-on-in-suspend;
275 regulator-suspend-microvolt = <1100000>;
276 };
277 };
278
279 avcc_1v8_s0: pldo-reg1 {
280 regulator-always-on;
281 regulator-boot-on;
282 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <1800000>;
284 regulator-ramp-delay = <12500>;
285 regulator-name = "avcc_1v8_s0";
286 regulator-state-mem {
287 regulator-off-in-suspend;
288 };
289 };
290
291 vdd1_1v8_ddr_s3: pldo-reg2 {
292 regulator-always-on;
293 regulator-boot-on;
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <1800000>;
296 regulator-ramp-delay = <12500>;
297 regulator-name = "vdd1_1v8_ddr_s3";
298 regulator-state-mem {
299 regulator-on-in-suspend;
300 regulator-suspend-microvolt = <1800000>;
301 };
302 };
303
304 vcc_1v8_s3: pldo-reg3 {
305 regulator-always-on;
306 regulator-boot-on;
307 regulator-min-microvolt = <1800000>;
308 regulator-max-microvolt = <1800000>;
309 regulator-ramp-delay = <12500>;
310 regulator-name = "vcc_1v8_s3";
311 regulator-state-mem {
312 regulator-on-in-suspend;
313 regulator-suspend-microvolt = <1800000>;
314 };
315 };
316
317 vcc_3v3_s0: pldo-reg4 {
318 regulator-always-on;
319 regulator-boot-on;
320 regulator-min-microvolt = <3300000>;
321 regulator-max-microvolt = <3300000>;
322 regulator-ramp-delay = <12500>;
323 regulator-name = "vcc_3v3_s0";
324 regulator-state-mem {
325 regulator-off-in-suspend;
326 };
327 };
328
329 vccio_sd_s0: pldo-reg5 {
330 regulator-always-on;
331 regulator-boot-on;
332 regulator-min-microvolt = <1800000>;
333 regulator-max-microvolt = <3300000>;
334 regulator-ramp-delay = <12500>;
335 regulator-name = "vccio_sd_s0";
336 regulator-state-mem {
337 regulator-off-in-suspend;
338 };
339 };
340
341 master_pldo6_s3: pldo-reg6 {
342 regulator-always-on;
343 regulator-boot-on;
344 regulator-min-microvolt = <1800000>;
345 regulator-max-microvolt = <1800000>;
346 regulator-name = "master_pldo6_s3";
347 regulator-state-mem {
348 regulator-on-in-suspend;
349 regulator-suspend-microvolt = <1800000>;
350 };
351 };
352
353 vdd_0v75_s3: nldo-reg1 {
354 regulator-always-on;
355 regulator-boot-on;
356 regulator-min-microvolt = <750000>;
357 regulator-max-microvolt = <750000>;
358 regulator-ramp-delay = <12500>;
359 regulator-name = "vdd_0v75_s3";
360 regulator-state-mem {
361 regulator-on-in-suspend;
362 regulator-suspend-microvolt = <750000>;
363 };
364 };
365
366 vdd2l_0v9_ddr_s3: nldo-reg2 {
367 regulator-always-on;
368 regulator-boot-on;
369 regulator-min-microvolt = <900000>;
370 regulator-max-microvolt = <900000>;
371 regulator-name = "vdd2l_0v9_ddr_s3";
372 regulator-state-mem {
373 regulator-on-in-suspend;
374 regulator-suspend-microvolt = <900000>;
375 };
376 };
377
378 master_nldo3: nldo-reg3 {
379 regulator-name = "master_nldo3";
380 regulator-state-mem {
381 regulator-off-in-suspend;
382 };
383 };
384
385 avdd_0v75_s0: nldo-reg4 {
386 regulator-always-on;
387 regulator-boot-on;
388 regulator-min-microvolt = <750000>;
389 regulator-max-microvolt = <750000>;
390 regulator-name = "avdd_0v75_s0";
391 regulator-state-mem {
392 regulator-off-in-suspend;
393 };
394 };
395
396 vdd_0v85_s0: nldo-reg5 {
397 regulator-always-on;
398 regulator-boot-on;
399 regulator-min-microvolt = <850000>;
400 regulator-max-microvolt = <850000>;
401 regulator-name = "vdd_0v85_s0";
402 regulator-state-mem {
403 regulator-off-in-suspend;
404 };
405 };
406 };
407 };
408 };