| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Synopsys DesignWare Universal Multi-Protocol Memory Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Krzysztof Kozlowski <krzk@kernel.org> |
| 11 | - Michal Simek <michal.simek@amd.com> |
| 12 | |
| 13 | description: | |
| 14 | Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of |
| 15 | working with the memory devices supporting up to (LP)DDR4 protocol. It can |
| 16 | be equipped with SEC/DEC ECC feature if DRAM data bus width is either |
| 17 | 16-bits or 32-bits or 64-bits wide. |
| 18 | |
| 19 | For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a |
| 20 | controller. It has an optional SEC/DEC ECC support in 64- and 32-bits |
| 21 | bus width configurations. |
| 22 | |
| 23 | properties: |
| 24 | compatible: |
| 25 | oneOf: |
| 26 | - deprecated: true |
| 27 | description: Synopsys DW uMCTL2 DDR controller v3.80a |
| 28 | const: snps,ddrc-3.80a |
| 29 | - description: Synopsys DW uMCTL2 DDR controller |
| 30 | const: snps,dw-umctl2-ddrc |
| 31 | - description: Xilinx ZynqMP DDR controller v2.40a |
| 32 | const: xlnx,zynqmp-ddrc-2.40a |
| 33 | |
| 34 | interrupts: |
| 35 | description: |
| 36 | DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":" |
| 37 | ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection, |
| 38 | Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the |
| 39 | signals merged before they reach the IRQ controller or have some of them |
| 40 | absent in case if the corresponding feature is unavailable/disabled. |
| 41 | minItems: 1 |
| 42 | maxItems: 5 |
| 43 | |
| 44 | interrupt-names: |
| 45 | minItems: 1 |
| 46 | maxItems: 5 |
| 47 | oneOf: |
| 48 | - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ |
| 49 | items: |
| 50 | - const: ecc |
| 51 | - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs |
| 52 | items: |
| 53 | enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] |
| 54 | |
| 55 | reg: |
| 56 | maxItems: 1 |
| 57 | |
| 58 | clocks: |
| 59 | description: |
| 60 | A standard set of the clock sources contains CSRs bus clock, AXI-ports |
| 61 | reference clock, DDRC core clock, Scrubber standalone clock |
| 62 | (synchronous to the DDRC clock). |
| 63 | minItems: 1 |
| 64 | maxItems: 4 |
| 65 | |
| 66 | clock-names: |
| 67 | minItems: 1 |
| 68 | maxItems: 4 |
| 69 | items: |
| 70 | enum: [ pclk, aclk, core, sbr ] |
| 71 | |
| 72 | resets: |
| 73 | description: |
| 74 | Each clock domain can have separate reset signal. |
| 75 | minItems: 1 |
| 76 | maxItems: 4 |
| 77 | |
| 78 | reset-names: |
| 79 | minItems: 1 |
| 80 | maxItems: 4 |
| 81 | items: |
| 82 | enum: [ prst, arst, core, sbr ] |
| 83 | |
| 84 | required: |
| 85 | - compatible |
| 86 | - reg |
| 87 | - interrupts |
| 88 | |
| 89 | additionalProperties: false |
| 90 | |
| 91 | examples: |
| 92 | - | |
| 93 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 94 | |
| 95 | memory-controller@fd070000 { |
| 96 | compatible = "xlnx,zynqmp-ddrc-2.40a"; |
| 97 | reg = <0xfd070000 0x30000>; |
| 98 | |
| 99 | interrupt-parent = <&gic>; |
| 100 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 101 | interrupt-names = "ecc"; |
| 102 | }; |
| 103 | - | |
| 104 | #include <dt-bindings/interrupt-controller/irq.h> |
| 105 | |
| 106 | memory-controller@3d400000 { |
| 107 | compatible = "snps,dw-umctl2-ddrc"; |
| 108 | reg = <0x3d400000 0x400000>; |
| 109 | |
| 110 | interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>, |
| 111 | <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>; |
| 112 | interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e"; |
| 113 | |
| 114 | clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>; |
| 115 | clock-names = "pclk", "aclk", "core", "sbr"; |
| 116 | }; |
| 117 | ... |