Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: ARM MHU Mailbox Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Jassi Brar <jaswinder.singh@linaro.org> |
| 11 | |
| 12 | description: | |
| 13 | The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3 |
| 14 | independent channels/links to communicate with remote processor(s). MHU links |
| 15 | are hardwired on a platform. A link raises interrupt for any received data. |
| 16 | However, there is no specified way of knowing if the sent data has been read |
| 17 | by the remote. This driver assumes the sender polls STAT register and the |
| 18 | remote clears it after having read the data. The last channel is specified to |
| 19 | be a 'Secure' resource, hence can't be used by Linux running NS. |
| 20 | |
| 21 | The MHU hardware also allows operations in doorbell mode. The MHU drives the |
| 22 | interrupt signal using a 32-bit register, with all 32-bits logically ORed |
| 23 | together. It provides a set of registers to enable software to set, clear and |
| 24 | check the status of each of the bits of this register independently. The use |
| 25 | of 32 bits per interrupt line enables software to provide more information |
| 26 | about the source of the interrupt. For example, each bit of the register can |
| 27 | be associated with a type of event that can contribute to raising the |
| 28 | interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote |
| 29 | processor. |
| 30 | |
| 31 | # We need a select here so we don't match all nodes with 'arm,primecell' |
| 32 | select: |
| 33 | properties: |
| 34 | compatible: |
| 35 | contains: |
| 36 | enum: |
| 37 | - arm,mhu |
| 38 | - arm,mhu-doorbell |
| 39 | required: |
| 40 | - compatible |
| 41 | |
| 42 | properties: |
| 43 | compatible: |
| 44 | oneOf: |
| 45 | - description: Data transfer mode |
| 46 | items: |
| 47 | - const: arm,mhu |
| 48 | - const: arm,primecell |
| 49 | |
| 50 | - description: Doorbell mode |
| 51 | items: |
| 52 | - const: arm,mhu-doorbell |
| 53 | - const: arm,primecell |
| 54 | |
| 55 | |
| 56 | reg: |
| 57 | maxItems: 1 |
| 58 | |
| 59 | interrupts: |
| 60 | minItems: 2 |
| 61 | items: |
| 62 | - description: low-priority non-secure |
| 63 | - description: high-priority non-secure |
| 64 | - description: Secure |
| 65 | |
| 66 | clocks: |
| 67 | maxItems: 1 |
| 68 | |
| 69 | clock-names: |
| 70 | items: |
| 71 | - const: apb_pclk |
| 72 | |
| 73 | '#mbox-cells': |
| 74 | description: | |
| 75 | Set to 1 in data transfer mode and represents index of the channel. |
| 76 | Set to 2 in doorbell mode and represents index of the channel and doorbell |
| 77 | number. |
| 78 | enum: [ 1, 2 ] |
| 79 | |
| 80 | required: |
| 81 | - compatible |
| 82 | - reg |
| 83 | - interrupts |
| 84 | - '#mbox-cells' |
| 85 | |
| 86 | additionalProperties: false |
| 87 | |
| 88 | examples: |
| 89 | # Data transfer mode. |
| 90 | - | |
| 91 | soc { |
| 92 | #address-cells = <2>; |
| 93 | #size-cells = <2>; |
| 94 | |
| 95 | mhuA: mailbox@2b1f0000 { |
| 96 | #mbox-cells = <1>; |
| 97 | compatible = "arm,mhu", "arm,primecell"; |
| 98 | reg = <0 0x2b1f0000 0 0x1000>; |
| 99 | interrupts = <0 36 4>, /* LP-NonSecure */ |
| 100 | <0 35 4>, /* HP-NonSecure */ |
| 101 | <0 37 4>; /* Secure */ |
| 102 | clocks = <&clock 0 2 1>; |
| 103 | clock-names = "apb_pclk"; |
| 104 | }; |
| 105 | }; |
| 106 | |
| 107 | firmware { |
| 108 | scpi { |
| 109 | compatible = "arm,scpi"; |
| 110 | mboxes = <&mhuA 1>; /* HP-NonSecure */ |
| 111 | shmem = <&cpu_scp_hpri>; /* HP-NonSecure */ |
| 112 | |
| 113 | scpi_devpd: power-controller { |
| 114 | compatible = "arm,scpi-power-domains"; |
| 115 | num-domains = <2>; |
| 116 | #power-domain-cells = <1>; |
| 117 | }; |
| 118 | }; |
| 119 | }; |
| 120 | |
| 121 | # Doorbell mode. |
| 122 | - | |
| 123 | soc { |
| 124 | #address-cells = <2>; |
| 125 | #size-cells = <2>; |
| 126 | |
| 127 | mhuB: mailbox@2b2f0000 { |
| 128 | #mbox-cells = <2>; |
| 129 | compatible = "arm,mhu-doorbell", "arm,primecell"; |
| 130 | reg = <0 0x2b2f0000 0 0x1000>; |
| 131 | interrupts = <0 36 4>, /* LP-NonSecure */ |
| 132 | <0 35 4>, /* HP-NonSecure */ |
| 133 | <0 37 4>; /* Secure */ |
| 134 | clocks = <&clock 0 2 1>; |
| 135 | clock-names = "apb_pclk"; |
| 136 | }; |
| 137 | }; |
| 138 | |
| 139 | firmware { |
| 140 | scmi { |
| 141 | compatible = "arm,scmi"; |
| 142 | mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */ |
| 143 | <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */ |
| 144 | mbox-names = "tx", "rx"; |
| 145 | shmem = <&cpu_scp_lpri0>, |
| 146 | <&cpu_scp_lpri1>; |
| 147 | |
| 148 | #address-cells = <1>; |
| 149 | #size-cells = <0>; |
| 150 | |
| 151 | scmi_devpd: protocol@11 { |
| 152 | reg = <0x11>; |
| 153 | #power-domain-cells = <1>; |
| 154 | }; |
| 155 | |
| 156 | scmi_dvfs: protocol@13 { |
| 157 | reg = <0x13>; |
| 158 | #clock-cells = <1>; |
| 159 | |
| 160 | mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */ |
| 161 | <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */ |
| 162 | mbox-names = "tx", "rx"; |
| 163 | shmem = <&cpu_scp_hpri0>, |
| 164 | <&cpu_scp_hpri1>; |
| 165 | }; |
| 166 | }; |
| 167 | }; |
| 168 | |
| 169 | ... |