| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller |
| 2 | |
| 3 | The MISC interrupt controller is a secondary controller for lower priority |
| 4 | interrupt. |
| 5 | |
| 6 | Required Properties: |
| 7 | - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or |
| 8 | "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" |
| 9 | - reg: Base address and size of the controllers memory area |
| 10 | - interrupts: Interrupt specifier for the controllers interrupt. |
| 11 | - interrupt-controller : Identifies the node as an interrupt controller |
| 12 | - #interrupt-cells : Specifies the number of cells needed to encode interrupt |
| 13 | source, should be 1 |
| 14 | |
| 15 | Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, |
| 16 | use ar7240 for all other SoCs. |
| 17 | |
| 18 | Please refer to interrupts.txt in this directory for details of the common |
| 19 | Interrupt Controllers bindings used by client devices. |
| 20 | |
| 21 | Example: |
| 22 | |
| 23 | interrupt-controller@18060010 { |
| 24 | compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; |
| 25 | reg = <0x18060010 0x4>; |
| 26 | |
| 27 | interrupt-parent = <&cpuintc>; |
| 28 | interrupts = <6>; |
| 29 | |
| 30 | interrupt-controller; |
| 31 | #interrupt-cells = <1>; |
| 32 | }; |
| 33 | |
| 34 | Another example: |
| 35 | |
| 36 | interrupt-controller@18060010 { |
| 37 | compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; |
| 38 | reg = <0x18060010 0x4>; |
| 39 | |
| 40 | interrupt-parent = <&cpuintc>; |
| 41 | interrupts = <6>; |
| 42 | |
| 43 | interrupt-controller; |
| 44 | #interrupt-cells = <1>; |
| 45 | }; |