| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Allwinner A10 Bus Gates Clock |
| 8 | |
| 9 | maintainers: |
| 10 | - Chen-Yu Tsai <wens@csie.org> |
| 11 | - Maxime Ripard <mripard@kernel.org> |
| 12 | |
| 13 | deprecated: true |
| 14 | |
| 15 | properties: |
| 16 | "#clock-cells": |
| 17 | const: 1 |
| 18 | description: > |
| 19 | This additional argument passed to that clock is the offset of |
| 20 | the bit controlling this particular gate in the register. |
| 21 | |
| 22 | compatible: |
| 23 | const: allwinner,sun8i-h3-bus-gates-clk |
| 24 | |
| 25 | reg: |
| 26 | maxItems: 1 |
| 27 | |
| 28 | clocks: |
| 29 | maxItems: 4 |
| 30 | |
| 31 | clock-names: |
| 32 | maxItems: 4 |
| 33 | description: > |
| 34 | The parent order must match the hardware programming order. |
| 35 | |
| 36 | clock-indices: |
| 37 | minItems: 1 |
| 38 | maxItems: 64 |
| 39 | |
| 40 | clock-output-names: |
| 41 | minItems: 1 |
| 42 | maxItems: 64 |
| 43 | |
| 44 | required: |
| 45 | - "#clock-cells" |
| 46 | - compatible |
| 47 | - reg |
| 48 | - clocks |
| 49 | - clock-indices |
| 50 | - clock-names |
| 51 | - clock-output-names |
| 52 | |
| 53 | additionalProperties: false |
| 54 | |
| 55 | examples: |
| 56 | - | |
| 57 | clk@1c20060 { |
| 58 | #clock-cells = <1>; |
| 59 | compatible = "allwinner,sun8i-h3-bus-gates-clk"; |
| 60 | reg = <0x01c20060 0x14>; |
| 61 | clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>; |
| 62 | clock-names = "ahb1", "ahb2", "apb1", "apb2"; |
| 63 | clock-indices = <5>, <6>, <8>, |
| 64 | <9>, <10>, <13>, |
| 65 | <14>, <17>, <18>, |
| 66 | <19>, <20>, |
| 67 | <21>, <23>, |
| 68 | <24>, <25>, |
| 69 | <26>, <27>, |
| 70 | <28>, <29>, |
| 71 | <30>, <31>, <32>, |
| 72 | <35>, <36>, <37>, |
| 73 | <40>, <41>, <43>, |
| 74 | <44>, <52>, <53>, |
| 75 | <54>, <64>, |
| 76 | <65>, <69>, <72>, |
| 77 | <76>, <77>, <78>, |
| 78 | <96>, <97>, <98>, |
| 79 | <112>, <113>, |
| 80 | <114>, <115>, |
| 81 | <116>, <128>, <135>; |
| 82 | clock-output-names = "bus_ce", "bus_dma", "bus_mmc0", |
| 83 | "bus_mmc1", "bus_mmc2", "bus_nand", |
| 84 | "bus_sdram", "bus_gmac", "bus_ts", |
| 85 | "bus_hstimer", "bus_spi0", |
| 86 | "bus_spi1", "bus_otg", |
| 87 | "bus_otg_ehci0", "bus_ehci1", |
| 88 | "bus_ehci2", "bus_ehci3", |
| 89 | "bus_otg_ohci0", "bus_ohci1", |
| 90 | "bus_ohci2", "bus_ohci3", "bus_ve", |
| 91 | "bus_lcd0", "bus_lcd1", "bus_deint", |
| 92 | "bus_csi", "bus_tve", "bus_hdmi", |
| 93 | "bus_de", "bus_gpu", "bus_msgbox", |
| 94 | "bus_spinlock", "bus_codec", |
| 95 | "bus_spdif", "bus_pio", "bus_ths", |
| 96 | "bus_i2s0", "bus_i2s1", "bus_i2s2", |
| 97 | "bus_i2c0", "bus_i2c1", "bus_i2c2", |
| 98 | "bus_uart0", "bus_uart1", |
| 99 | "bus_uart2", "bus_uart3", |
| 100 | "bus_scr", "bus_ephy", "bus_dbg"; |
| 101 | }; |
| 102 | |
| 103 | ... |