blob: d884785acbbe5f87e3f5f3be5017ba73d3acd7c8 [file] [log] [blame]
Masahiro Yamada52f0c512016-03-18 16:41:52 +09001/*
2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <debug_uart.h>
9#include <linux/io.h>
10#include <linux/serial_reg.h>
11
12#include "../soc-info.h"
13#include "debug-uart.h"
14
15#define UNIPHIER_UART_TX 0x00
16#define UNIPHIER_UART_LCR_MCR 0x10
17#define UNIPHIER_UART_LSR 0x14
18#define UNIPHIER_UART_LDR 0x24
19
20static void _debug_uart_putc(int c)
21{
22 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
23
24 while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
25 ;
26
27 writel(c, base + UNIPHIER_UART_TX);
28}
29
30void _debug_uart_init(void)
31{
32 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
33 unsigned int divisor;
34
35 switch (uniphier_get_soc_type()) {
36#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
37 case SOC_UNIPHIER_SLD3:
38 divisor = uniphier_sld3_debug_uart_init();
39 break;
40#endif
41#if defined(CONFIG_ARCH_UNIPHIER_LD4)
42 case SOC_UNIPHIER_LD4:
43 divisor = uniphier_ld4_debug_uart_init();
44 break;
45#endif
46#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
47 case SOC_UNIPHIER_PRO4:
48 divisor = uniphier_pro4_debug_uart_init();
49 break;
50#endif
51#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
52 case SOC_UNIPHIER_SLD8:
53 divisor = uniphier_sld8_debug_uart_init();
54 break;
55#endif
56#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
57 case SOC_UNIPHIER_PRO5:
58 divisor = uniphier_pro5_debug_uart_init();
59 break;
60#endif
61#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
62 case SOC_UNIPHIER_PXS2:
63 divisor = uniphier_pxs2_debug_uart_init();
64 break;
65#endif
66#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
67 case SOC_UNIPHIER_LD6B:
68 divisor = uniphier_ld6b_debug_uart_init();
69 break;
70#endif
71#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
72 case SOC_UNIPHIER_LD11:
73 case SOC_UNIPHIER_LD20:
74 divisor = uniphier_ld20_debug_uart_init();
75 break;
76#endif
77 default:
78 return;
79 }
80
81 writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
82
83 writel(divisor, base + UNIPHIER_UART_LDR);
84}
85DEBUG_UART_FUNCS