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git01.mediatek.com / filogic / uboot / 92e3d849925a873080213a402f3824c6675e6dba / . / board / lwmon5 / init.S
blob: e5207c2b40b5f1a0f26772b49dc0a76c420d39e0 [file] [log] [blame]
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]8 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]10#include <asm-offsets.h>
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]11#include <ppc_asm.tmpl>
12#include <config.h>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]13#include <asm/mmu.h>
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]14
15/**************************************************************************
16 * TLB TABLE
17 *
18 * This table is used by the cpu boot code to setup the initial tlb
19 * entries. Rather than make broad assumptions in the cpu source tree,
20 * this table lets each board set things up however they like.
21 *
22 * Pointer to the table is returned in r1
23 *
24 *************************************************************************/
25 .section .bootpg,"ax"
26 .globl tlbtab
27
28tlbtab:
29 tlbtab_start
30
31 /*
32 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
33 * speed up boot process. It is patched after relocation to enable SA_I
34 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]35 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]36
37 /*
38 * TLB entries for SDRAM are not needed on this platform.
39 * They are dynamically generated in the SPD DDR(2) detection
40 * routine.
41 */
42
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]43#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]44 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]45 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]46#endif
47
48 /* TLB-entry for PCI Memory */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]49 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
50 tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
51 tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
52 tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]53
54 /* TLB-entry for the FPGA Chip select 2 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]55 tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]56
57 /* TLB-entry for the FPGA Chip select 3 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]58 tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]59
60 /* TLB-entry for the LIME Controller */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]61 tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
62 tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
63 tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
64 tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]65
66 /* TLB-entry for Internal Registers & OCM */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]67 tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]68
69 /*TLB-entry PCI registers*/
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]70 tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]71
72 /* TLB-entry for peripherals */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]73 tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
Stefan Roeseade5a512007-06-15 08:18:01 +0200[diff] [blame]74
75 tlbtab_end