blob: 47afa263ea0290291c3e1faca71a93adeb63f391 [file] [log] [blame]
Patrice Chotardae19b812017-09-04 17:56:22 +02001/*
Patrice Chotard789ee0e2017-10-23 09:53:58 +02002 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
Patrice Chotardae19b812017-09-04 17:56:22 +02004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <fdtdec.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090012#include <linux/libfdt.h>
Patrice Chotardae19b812017-09-04 17:56:22 +020013#include <mmc.h>
14#include <reset.h>
15#include <asm/io.h>
16#include <asm/gpio.h>
17#include <linux/iopoll.h>
18
19struct stm32_sdmmc2_plat {
20 struct mmc_config cfg;
21 struct mmc mmc;
22};
23
24struct stm32_sdmmc2_priv {
25 fdt_addr_t base;
26 struct clk clk;
27 struct reset_ctl reset_ctl;
28 struct gpio_desc cd_gpio;
29 u32 clk_reg_msk;
30 u32 pwr_reg_msk;
31};
32
33struct stm32_sdmmc2_ctx {
34 u32 cache_start;
35 u32 cache_end;
36 u32 data_length;
37 bool dpsm_abort;
38};
39
40/* SDMMC REGISTERS OFFSET */
41#define SDMMC_POWER 0x00 /* SDMMC power control */
42#define SDMMC_CLKCR 0x04 /* SDMMC clock control */
43#define SDMMC_ARG 0x08 /* SDMMC argument */
44#define SDMMC_CMD 0x0C /* SDMMC command */
45#define SDMMC_RESP1 0x14 /* SDMMC response 1 */
46#define SDMMC_RESP2 0x18 /* SDMMC response 2 */
47#define SDMMC_RESP3 0x1C /* SDMMC response 3 */
48#define SDMMC_RESP4 0x20 /* SDMMC response 4 */
49#define SDMMC_DTIMER 0x24 /* SDMMC data timer */
50#define SDMMC_DLEN 0x28 /* SDMMC data length */
51#define SDMMC_DCTRL 0x2C /* SDMMC data control */
52#define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
53#define SDMMC_STA 0x34 /* SDMMC status */
54#define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
55#define SDMMC_MASK 0x3C /* SDMMC mask */
56#define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
57#define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
58
59/* SDMMC_POWER register */
60#define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
61#define SDMMC_POWER_VSWITCH BIT(2)
62#define SDMMC_POWER_VSWITCHEN BIT(3)
63#define SDMMC_POWER_DIRPOL BIT(4)
64
65/* SDMMC_CLKCR register */
66#define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
67#define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
68#define SDMMC_CLKCR_PWRSAV BIT(12)
69#define SDMMC_CLKCR_WIDBUS_4 BIT(14)
70#define SDMMC_CLKCR_WIDBUS_8 BIT(15)
71#define SDMMC_CLKCR_NEGEDGE BIT(16)
72#define SDMMC_CLKCR_HWFC_EN BIT(17)
73#define SDMMC_CLKCR_DDR BIT(18)
74#define SDMMC_CLKCR_BUSSPEED BIT(19)
Patrick Delaunaya36da362018-02-07 17:19:59 +010075#define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
76#define SDMMC_CLKCR_SELCLKRX_CK 0
77#define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
78#define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
Patrice Chotardae19b812017-09-04 17:56:22 +020079
80/* SDMMC_CMD register */
81#define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
82#define SDMMC_CMD_CMDTRANS BIT(6)
83#define SDMMC_CMD_CMDSTOP BIT(7)
84#define SDMMC_CMD_WAITRESP GENMASK(9, 8)
85#define SDMMC_CMD_WAITRESP_0 BIT(8)
86#define SDMMC_CMD_WAITRESP_1 BIT(9)
87#define SDMMC_CMD_WAITINT BIT(10)
88#define SDMMC_CMD_WAITPEND BIT(11)
89#define SDMMC_CMD_CPSMEN BIT(12)
90#define SDMMC_CMD_DTHOLD BIT(13)
91#define SDMMC_CMD_BOOTMODE BIT(14)
92#define SDMMC_CMD_BOOTEN BIT(15)
93#define SDMMC_CMD_CMDSUSPEND BIT(16)
94
95/* SDMMC_DCTRL register */
96#define SDMMC_DCTRL_DTEN BIT(0)
97#define SDMMC_DCTRL_DTDIR BIT(1)
98#define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
99#define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
100#define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
101#define SDMMC_DCTRL_RWSTART BIT(8)
102#define SDMMC_DCTRL_RWSTOP BIT(9)
103#define SDMMC_DCTRL_RWMOD BIT(10)
104#define SDMMC_DCTRL_SDMMCEN BIT(11)
105#define SDMMC_DCTRL_BOOTACKEN BIT(12)
106#define SDMMC_DCTRL_FIFORST BIT(13)
107
108/* SDMMC_STA register */
109#define SDMMC_STA_CCRCFAIL BIT(0)
110#define SDMMC_STA_DCRCFAIL BIT(1)
111#define SDMMC_STA_CTIMEOUT BIT(2)
112#define SDMMC_STA_DTIMEOUT BIT(3)
113#define SDMMC_STA_TXUNDERR BIT(4)
114#define SDMMC_STA_RXOVERR BIT(5)
115#define SDMMC_STA_CMDREND BIT(6)
116#define SDMMC_STA_CMDSENT BIT(7)
117#define SDMMC_STA_DATAEND BIT(8)
118#define SDMMC_STA_DHOLD BIT(9)
119#define SDMMC_STA_DBCKEND BIT(10)
120#define SDMMC_STA_DABORT BIT(11)
121#define SDMMC_STA_DPSMACT BIT(12)
122#define SDMMC_STA_CPSMACT BIT(13)
123#define SDMMC_STA_TXFIFOHE BIT(14)
124#define SDMMC_STA_RXFIFOHF BIT(15)
125#define SDMMC_STA_TXFIFOF BIT(16)
126#define SDMMC_STA_RXFIFOF BIT(17)
127#define SDMMC_STA_TXFIFOE BIT(18)
128#define SDMMC_STA_RXFIFOE BIT(19)
129#define SDMMC_STA_BUSYD0 BIT(20)
130#define SDMMC_STA_BUSYD0END BIT(21)
131#define SDMMC_STA_SDMMCIT BIT(22)
132#define SDMMC_STA_ACKFAIL BIT(23)
133#define SDMMC_STA_ACKTIMEOUT BIT(24)
134#define SDMMC_STA_VSWEND BIT(25)
135#define SDMMC_STA_CKSTOP BIT(26)
136#define SDMMC_STA_IDMATE BIT(27)
137#define SDMMC_STA_IDMABTC BIT(28)
138
139/* SDMMC_ICR register */
140#define SDMMC_ICR_CCRCFAILC BIT(0)
141#define SDMMC_ICR_DCRCFAILC BIT(1)
142#define SDMMC_ICR_CTIMEOUTC BIT(2)
143#define SDMMC_ICR_DTIMEOUTC BIT(3)
144#define SDMMC_ICR_TXUNDERRC BIT(4)
145#define SDMMC_ICR_RXOVERRC BIT(5)
146#define SDMMC_ICR_CMDRENDC BIT(6)
147#define SDMMC_ICR_CMDSENTC BIT(7)
148#define SDMMC_ICR_DATAENDC BIT(8)
149#define SDMMC_ICR_DHOLDC BIT(9)
150#define SDMMC_ICR_DBCKENDC BIT(10)
151#define SDMMC_ICR_DABORTC BIT(11)
152#define SDMMC_ICR_BUSYD0ENDC BIT(21)
153#define SDMMC_ICR_SDMMCITC BIT(22)
154#define SDMMC_ICR_ACKFAILC BIT(23)
155#define SDMMC_ICR_ACKTIMEOUTC BIT(24)
156#define SDMMC_ICR_VSWENDC BIT(25)
157#define SDMMC_ICR_CKSTOPC BIT(26)
158#define SDMMC_ICR_IDMATEC BIT(27)
159#define SDMMC_ICR_IDMABTCC BIT(28)
160#define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
161
162/* SDMMC_MASK register */
163#define SDMMC_MASK_CCRCFAILIE BIT(0)
164#define SDMMC_MASK_DCRCFAILIE BIT(1)
165#define SDMMC_MASK_CTIMEOUTIE BIT(2)
166#define SDMMC_MASK_DTIMEOUTIE BIT(3)
167#define SDMMC_MASK_TXUNDERRIE BIT(4)
168#define SDMMC_MASK_RXOVERRIE BIT(5)
169#define SDMMC_MASK_CMDRENDIE BIT(6)
170#define SDMMC_MASK_CMDSENTIE BIT(7)
171#define SDMMC_MASK_DATAENDIE BIT(8)
172#define SDMMC_MASK_DHOLDIE BIT(9)
173#define SDMMC_MASK_DBCKENDIE BIT(10)
174#define SDMMC_MASK_DABORTIE BIT(11)
175#define SDMMC_MASK_TXFIFOHEIE BIT(14)
176#define SDMMC_MASK_RXFIFOHFIE BIT(15)
177#define SDMMC_MASK_RXFIFOFIE BIT(17)
178#define SDMMC_MASK_TXFIFOEIE BIT(18)
179#define SDMMC_MASK_BUSYD0ENDIE BIT(21)
180#define SDMMC_MASK_SDMMCITIE BIT(22)
181#define SDMMC_MASK_ACKFAILIE BIT(23)
182#define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
183#define SDMMC_MASK_VSWENDIE BIT(25)
184#define SDMMC_MASK_CKSTOPIE BIT(26)
185#define SDMMC_MASK_IDMABTCIE BIT(28)
186
187/* SDMMC_IDMACTRL register */
188#define SDMMC_IDMACTRL_IDMAEN BIT(0)
189
190#define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
191
Patrice Chotardae19b812017-09-04 17:56:22 +0200192static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
193 struct mmc_data *data,
194 struct stm32_sdmmc2_ctx *ctx)
195{
196 u32 data_ctrl, idmabase0;
197
198 /* Configure the SDMMC DPSM (Data Path State Machine) */
199 data_ctrl = (__ilog2(data->blocksize) <<
200 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
201 SDMMC_DCTRL_DBLOCKSIZE;
202
203 if (data->flags & MMC_DATA_READ) {
204 data_ctrl |= SDMMC_DCTRL_DTDIR;
205 idmabase0 = (u32)data->dest;
206 } else {
207 idmabase0 = (u32)data->src;
208 }
209
210 /* Set the SDMMC Data TimeOut value */
211 writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER);
212
213 /* Set the SDMMC DataLength value */
214 writel(ctx->data_length, priv->base + SDMMC_DLEN);
215
216 /* Write to SDMMC DCTRL */
217 writel(data_ctrl, priv->base + SDMMC_DCTRL);
218
219 /* Cache align */
220 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
221 ctx->cache_end = roundup(idmabase0 + ctx->data_length,
222 ARCH_DMA_MINALIGN);
223
224 /*
225 * Flush data cache before DMA start (clean and invalidate)
226 * Clean also needed for read
227 * Avoid issue on buffer not cached-aligned
228 */
229 flush_dcache_range(ctx->cache_start, ctx->cache_end);
230
231 /* Enable internal DMA */
232 writel(idmabase0, priv->base + SDMMC_IDMABASE0);
233 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
234}
235
236static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
237 struct mmc_cmd *cmd, u32 cmd_param)
238{
239 if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN)
240 writel(0, priv->base + SDMMC_ARG);
241
242 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
243 if (cmd->resp_type & MMC_RSP_PRESENT) {
244 if (cmd->resp_type & MMC_RSP_136)
245 cmd_param |= SDMMC_CMD_WAITRESP;
246 else if (cmd->resp_type & MMC_RSP_CRC)
247 cmd_param |= SDMMC_CMD_WAITRESP_0;
248 else
249 cmd_param |= SDMMC_CMD_WAITRESP_1;
250 }
251
252 /* Clear flags */
253 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
254
255 /* Set SDMMC argument value */
256 writel(cmd->cmdarg, priv->base + SDMMC_ARG);
257
258 /* Set SDMMC command parameters */
259 writel(cmd_param, priv->base + SDMMC_CMD);
260}
261
262static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
263 struct mmc_cmd *cmd,
264 struct stm32_sdmmc2_ctx *ctx)
265{
266 u32 mask = SDMMC_STA_CTIMEOUT;
267 u32 status;
268 int ret;
269
270 if (cmd->resp_type & MMC_RSP_PRESENT) {
271 mask |= SDMMC_STA_CMDREND;
272 if (cmd->resp_type & MMC_RSP_CRC)
273 mask |= SDMMC_STA_CCRCFAIL;
274 } else {
275 mask |= SDMMC_STA_CMDSENT;
276 }
277
278 /* Polling status register */
279 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
Christophe Kerelloc9ab62c2017-10-09 17:02:28 +0200280 10000);
Patrice Chotardae19b812017-09-04 17:56:22 +0200281
282 if (ret < 0) {
283 debug("%s: timeout reading SDMMC_STA register\n", __func__);
284 ctx->dpsm_abort = true;
285 return ret;
286 }
287
288 /* Check status */
289 if (status & SDMMC_STA_CTIMEOUT) {
290 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
291 __func__, status, cmd->cmdidx);
292 ctx->dpsm_abort = true;
293 return -ETIMEDOUT;
294 }
295
296 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
297 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
298 __func__, status, cmd->cmdidx);
299 ctx->dpsm_abort = true;
300 return -EILSEQ;
301 }
302
303 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
304 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
305 if (cmd->resp_type & MMC_RSP_136) {
306 cmd->response[1] = readl(priv->base + SDMMC_RESP2);
307 cmd->response[2] = readl(priv->base + SDMMC_RESP3);
308 cmd->response[3] = readl(priv->base + SDMMC_RESP4);
309 }
310 }
311
312 return 0;
313}
314
315static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
316 struct mmc_cmd *cmd,
317 struct mmc_data *data,
318 struct stm32_sdmmc2_ctx *ctx)
319{
320 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
321 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
322 u32 status;
323
324 if (data->flags & MMC_DATA_READ)
325 mask |= SDMMC_STA_RXOVERR;
326 else
327 mask |= SDMMC_STA_TXUNDERR;
328
329 status = readl(priv->base + SDMMC_STA);
330 while (!(status & mask))
331 status = readl(priv->base + SDMMC_STA);
332
333 /*
334 * Need invalidate the dcache again to avoid any
335 * cache-refill during the DMA operations (pre-fetching)
336 */
337 if (data->flags & MMC_DATA_READ)
338 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
339
340 if (status & SDMMC_STA_DCRCFAIL) {
341 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
342 __func__, status, cmd->cmdidx);
343 if (readl(priv->base + SDMMC_DCOUNT))
344 ctx->dpsm_abort = true;
345 return -EILSEQ;
346 }
347
348 if (status & SDMMC_STA_DTIMEOUT) {
349 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
350 __func__, status, cmd->cmdidx);
351 ctx->dpsm_abort = true;
352 return -ETIMEDOUT;
353 }
354
355 if (status & SDMMC_STA_TXUNDERR) {
356 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
357 __func__, status, cmd->cmdidx);
358 ctx->dpsm_abort = true;
359 return -EIO;
360 }
361
362 if (status & SDMMC_STA_RXOVERR) {
363 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
364 __func__, status, cmd->cmdidx);
365 ctx->dpsm_abort = true;
366 return -EIO;
367 }
368
369 if (status & SDMMC_STA_IDMATE) {
370 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
371 __func__, status, cmd->cmdidx);
372 ctx->dpsm_abort = true;
373 return -EIO;
374 }
375
376 return 0;
377}
378
379static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
380 struct mmc_data *data)
381{
382 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
383 struct stm32_sdmmc2_ctx ctx;
384 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
385 int ret, retry = 3;
386
387retry_cmd:
388 ctx.data_length = 0;
389 ctx.dpsm_abort = false;
390
391 if (data) {
392 ctx.data_length = data->blocks * data->blocksize;
393 stm32_sdmmc2_start_data(priv, data, &ctx);
394 }
395
396 stm32_sdmmc2_start_cmd(priv, cmd, cmdat);
397
398 debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
399 __func__, cmd->cmdidx,
400 data ? ctx.data_length : 0, (unsigned int)data);
401
402 ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
403
404 if (data && !ret)
405 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
406
407 /* Clear flags */
408 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
409 if (data)
410 writel(0x0, priv->base + SDMMC_IDMACTRL);
411
412 /*
413 * To stop Data Path State Machine, a stop_transmission command
414 * shall be send on cmd or data errors.
415 */
416 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
417 struct mmc_cmd stop_cmd;
418
419 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
420 stop_cmd.cmdarg = 0;
421 stop_cmd.resp_type = MMC_RSP_R1b;
422
423 debug("%s: send STOP command to abort dpsm treatments\n",
424 __func__);
425
426 stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP);
427 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
428
429 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
430 }
431
432 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
433 printf("%s: cmd %d failed, retrying ...\n",
434 __func__, cmd->cmdidx);
435 retry--;
436 goto retry_cmd;
437 }
438
439 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
440
441 return ret;
442}
443
444static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
445{
446 /* Reset */
447 reset_assert(&priv->reset_ctl);
448 udelay(2);
449 reset_deassert(&priv->reset_ctl);
450
451 udelay(1000);
452
453 /* Set Power State to ON */
454 writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER);
455
456 /*
457 * 1ms: required power up waiting time before starting the
458 * SD initialization sequence
459 */
460 udelay(1000);
461}
462
463#define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
464static int stm32_sdmmc2_set_ios(struct udevice *dev)
465{
466 struct mmc *mmc = mmc_get_mmc_dev(dev);
467 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
468 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
469 struct mmc_config *cfg = &plat->cfg;
470 u32 desired = mmc->clock;
471 u32 sys_clock = clk_get_rate(&priv->clk);
472 u32 clk = 0;
473
474 debug("%s: bus_with = %d, clock = %d\n", __func__,
475 mmc->bus_width, mmc->clock);
476
477 if ((mmc->bus_width == 1) && (desired == cfg->f_min))
478 stm32_sdmmc2_pwron(priv);
479
480 /*
481 * clk_div = 0 => command and data generated on SDMMCCLK falling edge
482 * clk_div > 0 and NEGEDGE = 0 => command and data generated on
483 * SDMMCCLK rising edge
484 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
485 * SDMMCCLK falling edge
486 */
487 if (desired && ((sys_clock > desired) ||
488 IS_RISING_EDGE(priv->clk_reg_msk))) {
489 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
490 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
491 clk = SDMMC_CLKCR_CLKDIV_MAX;
492 }
493
494 if (mmc->bus_width == 4)
495 clk |= SDMMC_CLKCR_WIDBUS_4;
496 if (mmc->bus_width == 8)
497 clk |= SDMMC_CLKCR_WIDBUS_8;
498
Patrick Delaunay6eae43c2018-02-07 17:19:58 +0100499 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
500 priv->base + SDMMC_CLKCR);
Patrice Chotardae19b812017-09-04 17:56:22 +0200501
502 return 0;
503}
504
505static int stm32_sdmmc2_getcd(struct udevice *dev)
506{
507 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
508
509 debug("stm32_sdmmc2_getcd called\n");
510
511 if (dm_gpio_is_valid(&priv->cd_gpio))
512 return dm_gpio_get_value(&priv->cd_gpio);
513
514 return 1;
515}
516
517static const struct dm_mmc_ops stm32_sdmmc2_ops = {
518 .send_cmd = stm32_sdmmc2_send_cmd,
519 .set_ios = stm32_sdmmc2_set_ios,
520 .get_cd = stm32_sdmmc2_getcd,
521};
522
523static int stm32_sdmmc2_probe(struct udevice *dev)
524{
525 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
526 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
527 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
528 struct mmc_config *cfg = &plat->cfg;
529 int ret;
530
531 priv->base = dev_read_addr(dev);
532 if (priv->base == FDT_ADDR_T_NONE)
533 return -EINVAL;
534
535 if (dev_read_bool(dev, "st,negedge"))
536 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
537 if (dev_read_bool(dev, "st,dirpol"))
538 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
Patrick Delaunaya36da362018-02-07 17:19:59 +0100539 if (dev_read_bool(dev, "st,pin-ckin"))
540 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
Patrice Chotardae19b812017-09-04 17:56:22 +0200541
542 ret = clk_get_by_index(dev, 0, &priv->clk);
543 if (ret)
544 return ret;
545
546 ret = clk_enable(&priv->clk);
547 if (ret)
548 goto clk_free;
549
550 ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
551 if (ret)
552 goto clk_disable;
553
554 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
555 GPIOD_IS_IN);
556
557 cfg->f_min = 400000;
558 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
559 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
560 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
561 cfg->name = "STM32 SDMMC2";
562
563 cfg->host_caps = 0;
564 if (cfg->f_max > 25000000)
565 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
566
567 switch (dev_read_u32_default(dev, "bus-width", 1)) {
568 case 8:
569 cfg->host_caps |= MMC_MODE_8BIT;
570 case 4:
571 cfg->host_caps |= MMC_MODE_4BIT;
572 break;
573 case 1:
574 break;
575 default:
Masahiro Yamada81e10422017-09-16 14:10:41 +0900576 pr_err("invalid \"bus-width\" property, force to 1\n");
Patrice Chotardae19b812017-09-04 17:56:22 +0200577 }
578
579 upriv->mmc = &plat->mmc;
580
581 return 0;
582
583clk_disable:
584 clk_disable(&priv->clk);
585clk_free:
586 clk_free(&priv->clk);
587
588 return ret;
589}
590
591int stm32_sdmmc_bind(struct udevice *dev)
592{
593 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
594
595 return mmc_bind(dev, &plat->mmc, &plat->cfg);
596}
597
598static const struct udevice_id stm32_sdmmc2_ids[] = {
599 { .compatible = "st,stm32-sdmmc2" },
600 { }
601};
602
603U_BOOT_DRIVER(stm32_sdmmc2) = {
604 .name = "stm32_sdmmc2",
605 .id = UCLASS_MMC,
606 .of_match = stm32_sdmmc2_ids,
607 .ops = &stm32_sdmmc2_ops,
608 .probe = stm32_sdmmc2_probe,
609 .bind = stm32_sdmmc_bind,
610 .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
611 .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
612};