Marek Vasut | 5c30cf8 | 2023-05-31 20:24:34 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <clock_legacy.h> |
| 8 | #include <asm/io.h> |
| 9 | |
| 10 | #define CPGWPR 0xE6150900 |
| 11 | #define CPGWPCR 0xE6150904 |
| 12 | |
| 13 | /* PLL */ |
| 14 | #define PLL0CR 0xE61500D8 |
| 15 | #define PLL0_STC_MASK 0x7F000000 |
| 16 | #define PLL0_STC_OFFSET 24 |
| 17 | |
| 18 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
| 19 | void s_init(void) |
| 20 | { |
| 21 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
| 22 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
| 23 | u32 stc; |
| 24 | |
| 25 | /* Watchdog init */ |
| 26 | writel(0xA5A5A500, &rwdt->rwtcsra); |
| 27 | writel(0xA5A5A500, &swdt->swtcsra); |
| 28 | |
| 29 | /* CPU frequency setting. Set to 0.8GHz */ |
| 30 | stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET; |
| 31 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); |
| 32 | } |
| 33 | |
| 34 | int board_early_init_f(void) |
| 35 | { |
| 36 | /* Unlock CPG access */ |
| 37 | writel(0xA5A5FFFF, CPGWPR); |
| 38 | writel(0x5A5A0000, CPGWPCR); |
| 39 | |
| 40 | return 0; |
| 41 | } |