blob: 80877b61ffa525d0d6c4d068d26f85bbb6618735 [file] [log] [blame]
Dirk Eibach9a13d812010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/ppc4xx-gpio.h>
29
30#include <miiphy.h>
31
32#include "../common/fpga.h"
33
34#define PHYREG_CONTROL 0
35#define PHYREG_PAGE_ADDRESS 22
36#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
37#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
38
39enum {
40 REG_VERSIONS = 0x0002,
41 REG_FPGA_FEATURES = 0x0004,
42 REG_FPGA_VERSION = 0x0006,
43 REG_QUAD_SERDES_RESET = 0x0012,
44};
45
46enum {
47 UNITTYPE_CCD_SWITCH = 1,
48};
49
50enum {
51 HWVER_100 = 0,
52 HWVER_110 = 1,
53 HWVER_121 = 2,
54 HWVER_122 = 3,
55};
56
57int configure_gbit_phy(unsigned char addr)
58{
59 unsigned short value;
60
61 /* select page 2 */
62 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
63 PHYREG_PAGE_ADDRESS, 0x0002))
64 goto err_out;
65 /* disable SGMII autonegotiation */
66 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
67 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
68 goto err_out;
69 /* select page 0 */
70 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
71 PHYREG_PAGE_ADDRESS, 0x0000))
72 goto err_out;
73 /* switch from powerdown to normal operation */
74 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
75 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
76 goto err_out;
77 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
78 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
79 goto err_out;
80 /* reset phy so settings take effect */
81 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
82 PHYREG_CONTROL, 0x9140))
83 goto err_out;
84
85 return 0;
86
87err_out:
88 printf("Error writing to the PHY addr=%02x\n", addr);
89 return -1;
90}
91
92/*
93 * Check Board Identity:
94 */
95int checkboard(void)
96{
97 char *s = getenv("serial#");
98 u16 versions = fpga_get_reg(REG_VERSIONS);
99 u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
100 u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
101 unsigned unit_type;
102 unsigned hardware_version;
103 unsigned feature_channels;
104 unsigned feature_expansion;
105
106 unit_type = (versions & 0xf000) >> 12;
107 hardware_version = versions & 0x000f;
108 feature_channels = fpga_features & 0x007f;
109 feature_expansion = fpga_features & (1<<15);
110
111 printf("Board: ");
112
113 printf("CATCenter Io");
114
115 if (s != NULL) {
116 puts(", serial# ");
117 puts(s);
118 }
119 puts("\n ");
120
121 switch (unit_type) {
122 case UNITTYPE_CCD_SWITCH:
123 printf("CCD-Switch");
124 break;
125
126 default:
127 printf("UnitType %d(not supported)", unit_type);
128 break;
129 }
130
131 switch (hardware_version) {
132 case HWVER_100:
133 printf(" HW-Ver 1.00\n");
134 break;
135
136 case HWVER_110:
137 printf(" HW-Ver 1.10\n");
138 break;
139
140 case HWVER_121:
141 printf(" HW-Ver 1.21\n");
142 break;
143
144 case HWVER_122:
145 printf(" HW-Ver 1.22\n");
146 break;
147
148 default:
149 printf(" HW-Ver %d(not supported)\n",
150 hardware_version);
151 break;
152 }
153
154 printf(" FPGA V %d.%02d, features:",
155 fpga_version / 100, fpga_version % 100);
156
157 printf(" %d channel(s)", feature_channels);
158
159 printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
160
161 return 0;
162}
163
164/*
165 * setup Gbit PHYs
166 */
167int last_stage_init(void)
168{
169 unsigned int k;
170
171 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
172 bb_miiphy_read, bb_miiphy_write);
173
174 for (k = 0; k < 32; ++k)
175 configure_gbit_phy(k);
176
177 /* take fpga serdes blocks out of reset */
178 fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
179
180 return 0;
181}