wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 3 | * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
wdenk | ef5fe75 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 8 | #ifndef _U_BOOT_I386_H_ |
| 9 | #define _U_BOOT_I386_H_ 1 |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 10 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 11 | /* cpu/.../cpu.c */ |
Simon Glass | 19a8b12 | 2014-11-06 13:20:06 -0700 | [diff] [blame] | 12 | int arch_cpu_init(void); |
Graeme Russ | 121931c | 2011-02-12 15:11:35 +1100 | [diff] [blame] | 13 | int x86_cpu_init_f(void); |
Graeme Russ | 078395c | 2009-11-24 20:04:21 +1100 | [diff] [blame] | 14 | int cpu_init_f(void); |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 15 | void init_gd(gd_t *id, u64 *gdt_addr); |
| 16 | void setup_gdt(gd_t *id, u64 *gdt_addr); |
Graeme Russ | 6e25600 | 2011-12-27 22:46:43 +1100 | [diff] [blame] | 17 | int init_cache(void); |
Gabe Black | 846d08e | 2012-10-20 12:33:10 +0000 | [diff] [blame] | 18 | int cleanup_before_linux(void); |
Simon Glass | ace6cd8 | 2013-04-17 16:13:34 +0000 | [diff] [blame] | 19 | void panic_puts(const char *str); |
Graeme Russ | 7679d1f | 2009-02-24 21:14:45 +1100 | [diff] [blame] | 20 | |
| 21 | /* cpu/.../timer.c */ |
| 22 | void timer_isr(void *); |
| 23 | typedef void (timer_fnc_t) (void); |
| 24 | int register_timer_isr (timer_fnc_t *isr_func); |
Simon Glass | 11d7a5b | 2013-04-17 16:13:36 +0000 | [diff] [blame] | 25 | unsigned long get_tbclk_mhz(void); |
| 26 | void timer_set_base(uint64_t base); |
Simon Glass | 3e8b605 | 2013-04-17 16:13:39 +0000 | [diff] [blame] | 27 | int pcat_timer_init(void); |
Graeme Russ | 7679d1f | 2009-02-24 21:14:45 +1100 | [diff] [blame] | 28 | |
Simon Glass | 8aa7873 | 2014-11-06 13:20:05 -0700 | [diff] [blame] | 29 | /* Architecture specific DRAM init */ |
| 30 | int dram_init(void); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 31 | |
Graeme Russ | 77290ee | 2009-02-24 21:13:40 +1100 | [diff] [blame] | 32 | /* cpu/.../interrupts.c */ |
| 33 | int cpu_init_interrupts(void); |
| 34 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 35 | /* board/.../... */ |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 36 | int dram_init(void); |
| 37 | |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 38 | int cleanup_before_linux(void); |
| 39 | int x86_cleanup_before_linux(void); |
| 40 | void x86_enable_caches(void); |
| 41 | void x86_disable_caches(void); |
| 42 | int x86_init_cache(void); |
| 43 | void reset_cpu(ulong addr); |
| 44 | ulong board_get_usable_ram_top(ulong total_size); |
| 45 | void dram_init_banksize(void); |
Simon Glass | 543bb14 | 2014-11-10 18:00:26 -0700 | [diff] [blame] | 46 | int default_print_cpuinfo(void); |
Simon Glass | 8337433 | 2014-11-06 13:20:08 -0700 | [diff] [blame] | 47 | |
Graeme Russ | a8d06b4 | 2010-04-24 00:05:48 +1000 | [diff] [blame] | 48 | void setup_pcat_compatibility(void); |
| 49 | |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 50 | void isa_unmap_rom(u32 addr); |
| 51 | u32 isa_map_rom(u32 bus_addr, int size); |
| 52 | |
Graeme Russ | cbfce1d | 2011-04-13 19:43:28 +1000 | [diff] [blame] | 53 | /* arch/x86/lib/... */ |
wdenk | abda5ca | 2003-05-31 18:35:21 +0000 | [diff] [blame] | 54 | int video_bios_init(void); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 55 | |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 56 | void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); |
| 57 | void board_init_f_r(void) __attribute__ ((noreturn)); |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 58 | |
Vadim Bendebury | 1d82bac | 2012-10-23 18:04:32 +0000 | [diff] [blame] | 59 | /* Read the time stamp counter */ |
Simon Glass | 42081ce | 2013-06-11 11:14:52 -0700 | [diff] [blame] | 60 | static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void) |
Vadim Bendebury | 1d82bac | 2012-10-23 18:04:32 +0000 | [diff] [blame] | 61 | { |
| 62 | uint32_t high, low; |
| 63 | __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)); |
| 64 | return (((uint64_t)high) << 32) | low; |
| 65 | } |
| 66 | |
| 67 | /* board/... */ |
| 68 | void timer_set_tsc_base(uint64_t new_base); |
| 69 | uint64_t timer_get_tsc(void); |
| 70 | |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 71 | void quick_ram_check(void); |
| 72 | |
wdenk | ef5fe75 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 73 | #endif /* _U_BOOT_I386_H_ */ |