blob: c0f986784366dcaae54a1ba09754b0495269f5bf [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yang65922e02016-07-18 17:00:58 +08002/*
3 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 * Rockchip SD Host Controller Interface
Kever Yang65922e02016-07-18 17:00:58 +08006 */
7
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +08008#include <clk.h>
Kever Yang65922e02016-07-18 17:00:58 +08009#include <dm.h>
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +080010#include <dm/ofnode.h>
Kever Yangdd99a022017-02-13 17:38:57 +080011#include <dt-structs.h>
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +080012#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070013#include <linux/err.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090014#include <linux/libfdt.h>
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +080015#include <linux/iopoll.h>
Kever Yang65922e02016-07-18 17:00:58 +080016#include <malloc.h>
Kever Yangdd99a022017-02-13 17:38:57 +080017#include <mapmem.h>
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +080018#include "mmc_private.h"
Kever Yang65922e02016-07-18 17:00:58 +080019#include <sdhci.h>
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +080020#include <syscon.h>
21#include <asm/arch-rockchip/clock.h>
22#include <asm/arch-rockchip/hardware.h>
Kever Yang65922e02016-07-18 17:00:58 +080023
Alper Nebi Yasak6f198692022-03-15 20:46:28 +030024/* DWCMSHC specific Mode Select value */
25#define DWCMSHC_CTRL_HS400 0x7
Kever Yang65922e02016-07-18 17:00:58 +080026/* 400KHz is max freq for card ID etc. Use that as min */
27#define EMMC_MIN_FREQ 400000
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +080028#define KHz (1000)
29#define MHz (1000 * KHz)
30#define SDHCI_TUNING_LOOP_COUNT 40
31
32#define PHYCTRL_CALDONE_MASK 0x1
33#define PHYCTRL_CALDONE_SHIFT 0x6
34#define PHYCTRL_CALDONE_DONE 0x1
35#define PHYCTRL_DLLRDY_MASK 0x1
36#define PHYCTRL_DLLRDY_SHIFT 0x5
37#define PHYCTRL_DLLRDY_DONE 0x1
38#define PHYCTRL_FREQSEL_200M 0x0
39#define PHYCTRL_FREQSEL_50M 0x1
40#define PHYCTRL_FREQSEL_100M 0x2
41#define PHYCTRL_FREQSEL_150M 0x3
42#define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \
43 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
44 PHYCTRL_DLLRDY_DONE)
Kever Yang65922e02016-07-18 17:00:58 +080045
Alper Nebi Yasak9099d032022-03-15 20:46:27 +030046#define ARASAN_VENDOR_REGISTER 0x78
47#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
48
Jonas Karlman9168fbf2023-04-18 16:46:35 +000049/* Rockchip specific Registers */
50#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
Alper Nebi Yasak6f198692022-03-15 20:46:28 +030051#define DWCMSHC_CARD_IS_EMMC BIT(0)
52#define DWCMSHC_ENHANCED_STROBE BIT(8)
Jonas Karlman918d03e2025-04-07 22:46:55 +000053#define DWCMSHC_EMMC_AT_CTRL 0x540
54#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16)
55#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17
56#define EMMC_AT_CTRL_POST_CHANGE_DLY 19
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +080057#define DWCMSHC_EMMC_DLL_CTRL 0x800
58#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
59#define DWCMSHC_EMMC_DLL_RXCLK 0x804
60#define DWCMSHC_EMMC_DLL_TXCLK 0x808
61#define DWCMSHC_EMMC_DLL_STRBIN 0x80c
Jonas Karlmanee7115f2023-04-18 16:46:39 +000062#define DWCMSHC_EMMC_DLL_CMDOUT 0x810
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +080063#define DWCMSHC_EMMC_DLL_STATUS0 0x840
64#define DWCMSHC_EMMC_DLL_STATUS1 0x844
65#define DWCMSHC_EMMC_DLL_START BIT(0)
Jonas Karlman9168fbf2023-04-18 16:46:35 +000066#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
67#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +080068#define DWCMSHC_EMMC_DLL_START_POINT 16
69#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
70#define DWCMSHC_EMMC_DLL_INC_VALUE 2
71#define DWCMSHC_EMMC_DLL_INC 8
Vasily Khoruzhickb58c6832023-03-08 17:28:30 -080072#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +080073#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
Jonas Karlman9168fbf2023-04-18 16:46:35 +000074#define DLL_RXCLK_NO_INVERTER BIT(29)
75#define DLL_RXCLK_ORI_GATE BIT(31)
Jonas Karlmanf4f60052023-04-18 16:46:37 +000076#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
Jonas Karlman9168fbf2023-04-18 16:46:35 +000077#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
Jonas Karlmanee7115f2023-04-18 16:46:39 +000078#define DLL_TXCLK_NO_INVERTER BIT(29)
Jonas Karlmanf4f60052023-04-18 16:46:37 +000079#define DLL_STRBIN_TAPNUM_DEFAULT 0x4
Alper Nebi Yasak6f198692022-03-15 20:46:28 +030080#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
81#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
82#define DLL_STRBIN_DELAY_NUM_OFFSET 16
Jonas Karlmanf4f60052023-04-18 16:46:37 +000083#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x10
Jonas Karlmanee7115f2023-04-18 16:46:39 +000084#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
85#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
86#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
87#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
88#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
Alper Nebi Yasak6f198692022-03-15 20:46:28 +030089
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +080090#define DLL_LOCK_WO_TMOUT(x) \
91 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
92 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
93#define ROCKCHIP_MAX_CLKS 3
94
Jonas Karlmanee7115f2023-04-18 16:46:39 +000095#define FLAG_INVERTER_FLAG_IN_RXCLK BIT(0)
96
Kever Yang65922e02016-07-18 17:00:58 +080097struct rockchip_sdhc_plat {
98 struct mmc_config cfg;
99 struct mmc mmc;
100};
101
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800102struct rockchip_emmc_phy {
103 u32 emmcphy_con[7];
104 u32 reserved;
105 u32 emmcphy_status;
106};
107
Kever Yang65922e02016-07-18 17:00:58 +0800108struct rockchip_sdhc {
109 struct sdhci_host host;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800110 struct udevice *dev;
Kever Yang65922e02016-07-18 17:00:58 +0800111 void *base;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800112 struct rockchip_emmc_phy *phy;
113 struct clk emmc_clk;
114};
115
116struct sdhci_data {
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800117 int (*get_phy)(struct udevice *dev);
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300118
119 /**
120 * set_control_reg() - Set SDHCI control registers
121 *
122 * This is the set_control_reg() SDHCI operation that should be
123 * used for the hardware this driver data is associated with.
124 * Normally, this is used to set up control registers for
125 * voltage level and UHS speed mode.
126 *
127 * @host: SDHCI host structure
128 */
129 void (*set_control_reg)(struct sdhci_host *host);
130
131 /**
132 * set_ios_post() - Host specific hook after set_ios() calls
133 *
134 * This is the set_ios_post() SDHCI operation that should be
135 * used for the hardware this driver data is associated with.
136 * Normally, this is a hook that is called after sdhci_set_ios()
137 * that does any necessary host-specific configuration.
138 *
139 * @host: SDHCI host structure
140 * Return: 0 if successful, -ve on error
141 */
142 int (*set_ios_post)(struct sdhci_host *host);
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300143
Jonas Karlmanea312462023-04-18 16:46:29 +0000144 void (*set_clock)(struct sdhci_host *host, u32 div);
145 int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
146
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300147 /**
148 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
149 *
150 * This is the set_enhanced_strobe() SDHCI operation that should
151 * be used for the hardware this driver data is associated with.
152 * Normally, this is used to set any host-specific configuration
153 * necessary for HS400 ES.
154 *
155 * @host: SDHCI host structure
156 * Return: 0 if successful, -ve on error
157 */
158 int (*set_enhanced_strobe)(struct sdhci_host *host);
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000159
160 u32 flags;
161 u8 hs200_txclk_tapnum;
162 u8 hs400_txclk_tapnum;
Jonas Karlman0d9cc702025-04-07 22:46:53 +0000163 u8 hs400_cmdout_tapnum;
164 u8 hs400_strbin_tapnum;
165 u8 ddr50_strbin_delay_num;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800166};
167
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800168static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
169{
170 u32 caldone, dllrdy, freqsel;
171
172 writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
173 writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
174 writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
175
176 /*
177 * According to the user manual, calpad calibration
178 * cycle takes more than 2us without the minimal recommended
179 * value, so we may need a little margin here
180 */
181 udelay(3);
182 writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
183
184 /*
185 * According to the user manual, it asks driver to
186 * wait 5us for calpad busy trimming. But it seems that
187 * 5us of caldone isn't enough for all cases.
188 */
189 udelay(500);
190 caldone = readl(&phy->emmcphy_status);
191 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
192 if (caldone != PHYCTRL_CALDONE_DONE) {
193 printf("%s: caldone timeout.\n", __func__);
194 return;
195 }
196
197 /* Set the frequency of the DLL operation */
198 if (clock < 75 * MHz)
199 freqsel = PHYCTRL_FREQSEL_50M;
200 else if (clock < 125 * MHz)
201 freqsel = PHYCTRL_FREQSEL_100M;
202 else if (clock < 175 * MHz)
203 freqsel = PHYCTRL_FREQSEL_150M;
204 else
205 freqsel = PHYCTRL_FREQSEL_200M;
206
207 /* Set the frequency of the DLL operation */
208 writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
209 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
210
Yifeng Zhao58ec23b2021-10-15 16:41:27 +0800211 /* REN Enable on STRB Line for HS400 */
212 writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
213
Ariel D'Alessandro85573612022-04-12 10:31:35 -0300214 read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
215 5000, &phy->emmcphy_status);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800216}
217
218static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
219{
220 writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
221 writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
222}
223
224static int rk3399_emmc_get_phy(struct udevice *dev)
225{
226 struct rockchip_sdhc *priv = dev_get_priv(dev);
227 ofnode phy_node;
228 void *grf_base;
229 u32 grf_phy_offset, phandle;
230
231 phandle = dev_read_u32_default(dev, "phys", 0);
232 phy_node = ofnode_get_by_phandle(phandle);
233 if (!ofnode_valid(phy_node)) {
234 debug("Not found emmc phy device\n");
235 return -ENODEV;
236 }
237
238 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Haolin Li2ecb7492022-03-22 05:58:02 -0700239 if (IS_ERR_OR_NULL(grf_base)) {
Simon Glassbe4480d2024-09-20 09:24:41 +0200240 printf("%s: Get syscon grf failed\n", __func__);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800241 return -ENODEV;
242 }
243 grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
244
245 priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
246
247 return 0;
248}
249
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300250static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
251{
252 struct mmc *mmc = host->mmc;
253 u32 vendor;
254
255 vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
256 if (mmc->selected_mode == MMC_HS_400_ES)
257 vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
258 else
259 vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
260 sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
261
262 return 0;
263}
264
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300265static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800266{
267 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300268 struct mmc *mmc = host->mmc;
269 uint clock = mmc->tran_speed;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800270 int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
271
272 if (cycle_phy)
273 rk3399_emmc_phy_power_off(priv->phy);
274
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300275 sdhci_set_control_reg(host);
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300276
277 /*
278 * Reinitializing the device tries to set it to lower-speed modes
279 * first, which fails if the Enhanced Strobe bit is set, making
280 * the device impossible to use. Set the correct value here to
281 * let reinitialization attempts succeed.
282 */
283 if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
284 rk3399_sdhci_set_enhanced_strobe(host);
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300285};
286
287static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
288{
289 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
290 struct mmc *mmc = host->mmc;
291 uint clock = mmc->tran_speed;
292 int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
293
294 if (!clock)
295 clock = mmc->clock;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800296
297 if (cycle_phy)
298 rk3399_emmc_phy_power_on(priv->phy, clock);
299
300 return 0;
301}
302
Jonas Karlman78df6352023-04-20 15:55:15 +0000303static void rk3568_sdhci_set_clock(struct sdhci_host *host, u32 div)
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800304{
305 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
Jonas Karlman78df6352023-04-20 15:55:15 +0000306 struct mmc *mmc = host->mmc;
307 ulong rate;
308
309 rate = clk_set_rate(&priv->emmc_clk, mmc->clock);
310 if (IS_ERR_VALUE(rate))
311 printf("%s: Set clock rate failed: %ld\n", __func__, (long)rate);
312}
313
314static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable)
315{
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000316 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
317 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
318 struct mmc *mmc = host->mmc;
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800319 int val, ret;
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000320 u32 extra, txclk_tapnum;
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800321
Jonas Karlman68bc7022024-02-04 20:53:07 +0000322 if (!enable) {
323 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
Jonas Karlman78df6352023-04-20 15:55:15 +0000324 return 0;
Jonas Karlman68bc7022024-02-04 20:53:07 +0000325 }
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800326
327 if (clock >= 100 * MHz) {
328 /* reset DLL */
329 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
330 udelay(1);
331 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
332
Jonas Karlman918d03e2025-04-07 22:46:55 +0000333 extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
334 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
335 EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
336 sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
337
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800338 /* Init DLL settings */
339 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
340 DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
341 DWCMSHC_EMMC_DLL_START;
342 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
343
Ariel D'Alessandro85573612022-04-12 10:31:35 -0300344 ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
345 500,
346 host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0);
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800347 if (ret)
348 return ret;
349
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000350 extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
351 if (data->flags & FLAG_INVERTER_FLAG_IN_RXCLK)
352 extra |= DLL_RXCLK_NO_INVERTER;
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800353 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
354
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000355 txclk_tapnum = data->hs200_txclk_tapnum;
356 if (mmc->selected_mode == MMC_HS_400 ||
357 mmc->selected_mode == MMC_HS_400_ES) {
358 txclk_tapnum = data->hs400_txclk_tapnum;
359
360 extra = DLL_CMDOUT_SRC_CLK_NEG |
361 DLL_CMDOUT_BOTH_CLK_EDGE |
362 DWCMSHC_EMMC_DLL_DLYENA |
Jonas Karlman0d9cc702025-04-07 22:46:53 +0000363 data->hs400_cmdout_tapnum |
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000364 DLL_CMDOUT_TAPNUM_FROM_SW;
365 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
366 }
367
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800368 extra = DWCMSHC_EMMC_DLL_DLYENA |
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000369 DLL_TXCLK_TAPNUM_FROM_SW |
370 DLL_TXCLK_NO_INVERTER |
371 txclk_tapnum;
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800372 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
373
374 extra = DWCMSHC_EMMC_DLL_DLYENA |
Jonas Karlman0d9cc702025-04-07 22:46:53 +0000375 data->hs400_strbin_tapnum |
Alper Nebi Yasak6f198692022-03-15 20:46:28 +0300376 DLL_STRBIN_TAPNUM_FROM_SW;
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800377 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
378 } else {
Vasily Khoruzhickb58c6832023-03-08 17:28:30 -0800379 /*
380 * Disable DLL and reset both of sample and drive clock.
381 * The bypass bit and start bit need to be set if DLL is not locked.
382 */
Jonas Karlman9168fbf2023-04-18 16:46:35 +0000383 extra = DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START;
384 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
Vasily Khoruzhickb58c6832023-03-08 17:28:30 -0800385 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800386 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000387 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CMDOUT);
Alper Nebi Yasak6f198692022-03-15 20:46:28 +0300388 /*
389 * Before switching to hs400es mode, the driver will enable
390 * enhanced strobe first. PHY needs to configure the parameters
391 * of enhanced strobe first.
392 */
393 extra = DWCMSHC_EMMC_DLL_DLYENA |
394 DLL_STRBIN_DELAY_NUM_SEL |
Jonas Karlman0d9cc702025-04-07 22:46:53 +0000395 data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
Alper Nebi Yasak6f198692022-03-15 20:46:28 +0300396 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800397 }
398
399 return 0;
400}
401
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300402static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800403{
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800404 struct mmc *mmc = host->mmc;
Jonas Karlmanb42bdde2024-04-10 14:30:50 +0000405 struct rockchip_sdhc_plat *plat = dev_get_plat(mmc->dev);
406 struct mmc_config *cfg = &plat->cfg;
Jonas Karlman9168fbf2023-04-18 16:46:35 +0000407 u32 reg;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800408
Jonas Karlmandbe75fbe2023-04-18 16:46:33 +0000409 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
410 reg &= ~SDHCI_CTRL_UHS_MASK;
411
412 switch (mmc->selected_mode) {
413 case UHS_SDR25:
414 case MMC_HS:
415 case MMC_HS_52:
416 reg |= SDHCI_CTRL_UHS_SDR25;
417 break;
418 case UHS_SDR50:
419 reg |= SDHCI_CTRL_UHS_SDR50;
420 break;
421 case UHS_DDR50:
422 case MMC_DDR_52:
423 reg |= SDHCI_CTRL_UHS_DDR50;
424 break;
425 case UHS_SDR104:
426 case MMC_HS_200:
427 reg |= SDHCI_CTRL_UHS_SDR104;
428 break;
429 case MMC_HS_400:
430 case MMC_HS_400_ES:
Alper Nebi Yasak6f198692022-03-15 20:46:28 +0300431 reg |= DWCMSHC_CTRL_HS400;
Jonas Karlmandbe75fbe2023-04-18 16:46:33 +0000432 break;
433 default:
434 reg |= SDHCI_CTRL_UHS_SDR12;
435 }
Alper Nebi Yasak6f198692022-03-15 20:46:28 +0300436
Jonas Karlmandbe75fbe2023-04-18 16:46:33 +0000437 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
438
Jonas Karlman9168fbf2023-04-18 16:46:35 +0000439 reg = sdhci_readw(host, DWCMSHC_EMMC_EMMC_CTRL);
Jonas Karlmandbe75fbe2023-04-18 16:46:33 +0000440
441 if (IS_MMC(mmc))
Alper Nebi Yasak6f198692022-03-15 20:46:28 +0300442 reg |= DWCMSHC_CARD_IS_EMMC;
Jonas Karlmandbe75fbe2023-04-18 16:46:33 +0000443 else
444 reg &= ~DWCMSHC_CARD_IS_EMMC;
445
446 if (mmc->selected_mode == MMC_HS_400_ES)
447 reg |= DWCMSHC_ENHANCED_STROBE;
448 else
449 reg &= ~DWCMSHC_ENHANCED_STROBE;
450
Jonas Karlman9168fbf2023-04-18 16:46:35 +0000451 sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800452
Jonas Karlmanb42bdde2024-04-10 14:30:50 +0000453 /*
454 * Reading more than 4 blocks with a single CMD18 command in PIO mode
455 * triggers Data End Bit Error using a slower mode than HS200. Limit to
456 * reading max 4 blocks in one command when using PIO mode.
457 */
458 if (!(host->flags & USE_DMA)) {
459 if (mmc->selected_mode == MMC_HS_200 ||
460 mmc->selected_mode == MMC_HS_400 ||
461 mmc->selected_mode == MMC_HS_400_ES)
462 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
463 else
464 cfg->b_max = 4;
465 }
466
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800467 return 0;
468}
469
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300470static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
471{
472 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
473 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
474
475 if (data->set_control_reg)
476 data->set_control_reg(host);
477}
478
479static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
480{
481 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
482 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
483
484 if (data->set_ios_post)
485 return data->set_ios_post(host);
486
487 return 0;
488}
489
Jonas Karlmanea312462023-04-18 16:46:29 +0000490static void rockchip_sdhci_set_clock(struct sdhci_host *host, u32 div)
491{
492 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
493 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
494
495 if (data->set_clock)
496 data->set_clock(host, div);
497}
498
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800499static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
500{
Jonas Karlman99f38882023-04-18 16:46:26 +0000501 struct rockchip_sdhc *priv = dev_get_priv(mmc->dev);
502 struct sdhci_host *host = &priv->host;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800503 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
504 struct mmc_cmd cmd;
505 u32 ctrl, blk_size;
Jonas Karlmanfdea3712023-04-18 16:46:31 +0000506 int ret;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800507
508 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
509 ctrl |= SDHCI_CTRL_EXEC_TUNING;
510 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
511
512 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800513
514 blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
Jonas Karlmanfdea3712023-04-18 16:46:31 +0000515 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800516 blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
517 sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
518 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
519
520 cmd.cmdidx = opcode;
521 cmd.resp_type = MMC_RSP_R1;
522 cmd.cmdarg = 0;
523
524 do {
Jonas Karlmanfdea3712023-04-18 16:46:31 +0000525 ret = mmc_send_cmd(mmc, &cmd, NULL);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800526 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
Jonas Karlmanfdea3712023-04-18 16:46:31 +0000527 if (ret || tuning_loop_counter-- == 0)
528 break;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800529 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
530
Jonas Karlmanfdea3712023-04-18 16:46:31 +0000531 if (ret || tuning_loop_counter < 0 || !(ctrl & SDHCI_CTRL_TUNED_CLK)) {
532 if (!ret)
533 ret = -EIO;
534 printf("%s: Tuning failed: %d\n", __func__, ret);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800535
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800536 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
Jonas Karlmanfdea3712023-04-18 16:46:31 +0000537 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
538 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800539 }
540
541 /* Enable only interrupts served by the SD controller */
542 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800543
544 return ret;
545}
546
Jonas Karlmanea312462023-04-18 16:46:29 +0000547static int rockchip_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enable)
548{
549 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
550 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
551
552 if (data->config_dll)
553 return data->config_dll(host, clock, enable);
554
555 return 0;
556}
557
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300558static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
559{
560 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
561 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
562
563 if (data->set_enhanced_strobe)
564 return data->set_enhanced_strobe(host);
565
Jonas Karlmandd2707f2023-04-18 16:46:34 +0000566 return 0;
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300567}
568
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800569static struct sdhci_ops rockchip_sdhci_ops = {
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300570 .set_control_reg = rockchip_sdhci_set_control_reg,
Jonas Karlmanea312462023-04-18 16:46:29 +0000571 .set_ios_post = rockchip_sdhci_set_ios_post,
572 .set_clock = rockchip_sdhci_set_clock,
573 .platform_execute_tuning = rockchip_sdhci_execute_tuning,
574 .config_dll = rockchip_sdhci_config_dll,
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300575 .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
Kever Yang65922e02016-07-18 17:00:58 +0800576};
577
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800578static int rockchip_sdhci_probe(struct udevice *dev)
Kever Yang65922e02016-07-18 17:00:58 +0800579{
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800580 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
Kever Yang65922e02016-07-18 17:00:58 +0800581 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -0700582 struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
Jonas Karlman99f38882023-04-18 16:46:26 +0000583 struct rockchip_sdhc *priv = dev_get_priv(dev);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800584 struct mmc_config *cfg = &plat->cfg;
Jonas Karlman99f38882023-04-18 16:46:26 +0000585 struct sdhci_host *host = &priv->host;
Simon Glass979f26d2024-09-20 09:24:40 +0200586 struct clk *clk = &priv->emmc_clk;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800587 int ret;
Kever Yang9ea1fdf2016-12-28 11:32:35 +0800588
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800589 host->max_clk = cfg->f_max;
Simon Glass979f26d2024-09-20 09:24:40 +0200590 ret = clk_get_by_index(dev, 0, clk);
Kever Yang9ea1fdf2016-12-28 11:32:35 +0800591 if (!ret) {
Simon Glass979f26d2024-09-20 09:24:40 +0200592 ret = clk_set_rate(clk, host->max_clk);
Kever Yang9ea1fdf2016-12-28 11:32:35 +0800593 if (IS_ERR_VALUE(ret))
594 printf("%s clk set rate fail!\n", __func__);
Simon Glass979f26d2024-09-20 09:24:40 +0200595 } else if (ret != -ENOSYS) {
Kever Yang9ea1fdf2016-12-28 11:32:35 +0800596 printf("%s fail to get clk\n", __func__);
597 }
Kever Yang65922e02016-07-18 17:00:58 +0800598
Jonas Karlman99f38882023-04-18 16:46:26 +0000599 priv->dev = dev;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800600
601 if (data->get_phy) {
602 ret = data->get_phy(dev);
603 if (ret)
604 return ret;
605 }
606
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800607 host->ops = &rockchip_sdhci_ops;
Kever Yang65922e02016-07-18 17:00:58 +0800608 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
609
Kever Yang65922e02016-07-18 17:00:58 +0800610 host->mmc = &plat->mmc;
Jonas Karlman99f38882023-04-18 16:46:26 +0000611 host->mmc->priv = &priv->host;
Kever Yang65922e02016-07-18 17:00:58 +0800612 host->mmc->dev = dev;
613 upriv->mmc = host->mmc;
614
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800615 ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
Kever Yang36d9bf82019-07-19 18:01:11 +0800616 if (ret)
617 return ret;
618
Jonas Karlman5d259362023-04-18 16:46:45 +0000619 /*
Jonas Karlmanf79c5372023-05-06 17:41:11 +0000620 * Disable use of DMA and force use of PIO mode in SPL to fix an issue
621 * where loading part of TF-A into SRAM using DMA silently fails.
622 */
Simon Glass7ec24132024-09-29 19:49:48 -0600623 if (IS_ENABLED(CONFIG_XPL_BUILD) &&
Jonas Karlmanf79c5372023-05-06 17:41:11 +0000624 dev_read_bool(dev, "u-boot,spl-fifo-mode"))
625 host->flags &= ~USE_DMA;
626
Kever Yang65922e02016-07-18 17:00:58 +0800627 return sdhci_probe(dev);
628}
629
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800630static int rockchip_sdhci_of_to_plat(struct udevice *dev)
Kever Yang65922e02016-07-18 17:00:58 +0800631{
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800632 struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
Jonas Karlman99f38882023-04-18 16:46:26 +0000633 struct rockchip_sdhc *priv = dev_get_priv(dev);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800634 struct mmc_config *cfg = &plat->cfg;
Jonas Karlman99f38882023-04-18 16:46:26 +0000635 struct sdhci_host *host = &priv->host;
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800636 int ret;
Kever Yang65922e02016-07-18 17:00:58 +0800637
638 host->name = dev->name;
Philipp Tomsichdbb28282017-09-11 22:04:21 +0200639 host->ioaddr = dev_read_addr_ptr(dev);
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800640
641 ret = mmc_of_parse(dev, cfg);
642 if (ret)
643 return ret;
Kever Yang65922e02016-07-18 17:00:58 +0800644
645 return 0;
646}
647
648static int rockchip_sdhci_bind(struct udevice *dev)
649{
Simon Glassfa20e932020-12-03 16:55:20 -0700650 struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
Kever Yang65922e02016-07-18 17:00:58 +0800651
Masahiro Yamadacdb67f32016-09-06 22:17:32 +0900652 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Kever Yang65922e02016-07-18 17:00:58 +0800653}
654
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800655static const struct sdhci_data rk3399_data = {
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800656 .get_phy = rk3399_emmc_get_phy,
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300657 .set_control_reg = rk3399_sdhci_set_control_reg,
658 .set_ios_post = rk3399_sdhci_set_ios_post,
Alper Nebi Yasak9099d032022-03-15 20:46:27 +0300659 .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800660};
661
Jonas Karlman204ada62025-04-07 22:46:54 +0000662static const struct sdhci_data rk3528_data = {
663 .set_ios_post = rk3568_sdhci_set_ios_post,
664 .set_clock = rk3568_sdhci_set_clock,
665 .config_dll = rk3568_sdhci_config_dll,
666 .hs200_txclk_tapnum = 0xc,
667 .hs400_txclk_tapnum = 0x6,
668 .hs400_cmdout_tapnum = 0x6,
669 .hs400_strbin_tapnum = 0x3,
670 .ddr50_strbin_delay_num = 0xa,
671};
672
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800673static const struct sdhci_data rk3568_data = {
Alper Nebi Yasak676a5a52022-01-29 01:42:37 +0300674 .set_ios_post = rk3568_sdhci_set_ios_post,
Jonas Karlman78df6352023-04-20 15:55:15 +0000675 .set_clock = rk3568_sdhci_set_clock,
676 .config_dll = rk3568_sdhci_config_dll,
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000677 .flags = FLAG_INVERTER_FLAG_IN_RXCLK,
678 .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
Jonas Karlman68bc7022024-02-04 20:53:07 +0000679 .hs400_txclk_tapnum = 0x8,
Jonas Karlman0d9cc702025-04-07 22:46:53 +0000680 .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
681 .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
682 .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800683};
684
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000685static const struct sdhci_data rk3588_data = {
686 .set_ios_post = rk3568_sdhci_set_ios_post,
687 .set_clock = rk3568_sdhci_set_clock,
688 .config_dll = rk3568_sdhci_config_dll,
689 .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
Jonas Karlman68bc7022024-02-04 20:53:07 +0000690 .hs400_txclk_tapnum = 0x9,
Jonas Karlman0d9cc702025-04-07 22:46:53 +0000691 .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
692 .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
693 .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000694};
695
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800696static const struct udevice_id sdhci_ids[] = {
697 {
698 .compatible = "arasan,sdhci-5.1",
699 .data = (ulong)&rk3399_data,
700 },
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800701 {
Jonas Karlman204ada62025-04-07 22:46:54 +0000702 .compatible = "rockchip,rk3528-dwcmshc",
703 .data = (ulong)&rk3528_data,
704 },
705 {
Yifeng Zhaoe5dddfa2021-06-29 16:24:42 +0800706 .compatible = "rockchip,rk3568-dwcmshc",
707 .data = (ulong)&rk3568_data,
708 },
Jonas Karlmanee7115f2023-04-18 16:46:39 +0000709 {
710 .compatible = "rockchip,rk3588-dwcmshc",
711 .data = (ulong)&rk3588_data,
712 },
Kever Yang65922e02016-07-18 17:00:58 +0800713 { }
714};
715
716U_BOOT_DRIVER(arasan_sdhci_drv) = {
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800717 .name = "rockchip_sdhci_5_1",
Kever Yang65922e02016-07-18 17:00:58 +0800718 .id = UCLASS_MMC,
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800719 .of_match = sdhci_ids,
720 .of_to_plat = rockchip_sdhci_of_to_plat,
Kever Yang65922e02016-07-18 17:00:58 +0800721 .ops = &sdhci_ops,
722 .bind = rockchip_sdhci_bind,
Yifeng Zhao5c2a5ab2021-06-29 16:24:41 +0800723 .probe = rockchip_sdhci_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700724 .priv_auto = sizeof(struct rockchip_sdhc),
Simon Glass71fa5b42020-12-03 16:55:18 -0700725 .plat_auto = sizeof(struct rockchip_sdhc_plat),
Kever Yang65922e02016-07-18 17:00:58 +0800726};