Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 4 | * |
| 5 | * Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 8 | #include <log.h> |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 9 | #include <pci.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 11 | #include <asm/pci.h> |
| 12 | #include <asm/pirq_routing.h> |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 13 | |
Simon Glass | 25271ae | 2019-12-06 21:42:15 -0700 | [diff] [blame] | 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
Simon Glass | 27a6eaa | 2017-01-16 07:04:18 -0700 | [diff] [blame] | 16 | static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap, |
| 17 | bool irq_already_routed[]) |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 18 | { |
| 19 | int i, link; |
| 20 | u8 irq = 0; |
| 21 | |
| 22 | /* IRQ sharing starts from IRQ#3 */ |
| 23 | for (i = 3; i < 16; i++) { |
| 24 | /* Can we assign this IRQ? */ |
| 25 | if (!((bitmap >> i) & 1)) |
| 26 | continue; |
| 27 | |
| 28 | /* We can, now let's assume we can use this IRQ */ |
| 29 | irq = i; |
| 30 | |
| 31 | /* Have we already routed it? */ |
| 32 | if (irq_already_routed[irq]) |
| 33 | continue; |
| 34 | |
| 35 | for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) { |
Bin Meng | a5a2003 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 36 | if (pirq_check_irq_routed(dev, link, irq)) { |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 37 | irq_already_routed[irq] = true; |
| 38 | break; |
| 39 | } |
| 40 | } |
| 41 | |
| 42 | /* If it's not yet routed, use it */ |
| 43 | if (!irq_already_routed[irq]) { |
| 44 | irq_already_routed[irq] = true; |
| 45 | break; |
| 46 | } |
| 47 | |
| 48 | /* But if it was already routed, try the next one */ |
| 49 | } |
| 50 | |
| 51 | /* Now we get our IRQ */ |
| 52 | return irq; |
| 53 | } |
| 54 | |
Bin Meng | a5a2003 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 55 | void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num) |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 56 | { |
| 57 | unsigned char irq_slot[MAX_INTX_ENTRIES]; |
| 58 | unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; |
Simon Glass | 27a6eaa | 2017-01-16 07:04:18 -0700 | [diff] [blame] | 59 | bool irq_already_routed[16]; |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 60 | int i, intx; |
| 61 | |
| 62 | memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); |
Simon Glass | 27a6eaa | 2017-01-16 07:04:18 -0700 | [diff] [blame] | 63 | memset(irq_already_routed, '\0', sizeof(irq_already_routed)); |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 64 | |
| 65 | /* Set PCI IRQs */ |
| 66 | for (i = 0; i < num; i++) { |
| 67 | debug("PIRQ Entry %d Dev: %d.%x.%d\n", i, |
| 68 | irq->bus, irq->devfn >> 3, irq->devfn & 7); |
| 69 | |
| 70 | for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { |
| 71 | int link = irq->irq[intx].link; |
| 72 | int bitmap = irq->irq[intx].bitmap; |
| 73 | int irq = 0; |
| 74 | |
| 75 | debug("INT%c link: %x bitmap: %x ", |
| 76 | 'A' + intx, link, bitmap); |
| 77 | |
| 78 | if (!bitmap || !link) { |
| 79 | debug("not routed\n"); |
| 80 | irq_slot[intx] = irq; |
| 81 | continue; |
| 82 | } |
| 83 | |
| 84 | /* translate link value to link number */ |
Bin Meng | a5a2003 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 85 | link = pirq_translate_link(dev, link); |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 86 | |
| 87 | /* yet not routed */ |
| 88 | if (!pirq[link]) { |
Simon Glass | 27a6eaa | 2017-01-16 07:04:18 -0700 | [diff] [blame] | 89 | irq = pirq_get_next_free_irq(dev, pirq, bitmap, |
| 90 | irq_already_routed); |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 91 | pirq[link] = irq; |
| 92 | } else { |
| 93 | irq = pirq[link]; |
| 94 | } |
| 95 | |
| 96 | debug("IRQ: %d\n", irq); |
| 97 | irq_slot[intx] = irq; |
| 98 | |
| 99 | /* Assign IRQ in the interrupt router */ |
Bin Meng | a5a2003 | 2016-02-01 01:40:51 -0800 | [diff] [blame] | 100 | pirq_assign_irq(dev, link, irq); |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 101 | } |
| 102 | |
| 103 | /* Bus, device, slots IRQs for {A,B,C,D} */ |
Bin Meng | da5d463 | 2015-07-15 16:23:40 +0800 | [diff] [blame] | 104 | pci_assign_irqs(irq->bus, irq->devfn >> 3, irq_slot); |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 105 | |
| 106 | irq++; |
| 107 | } |
| 108 | |
| 109 | for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++) |
| 110 | debug("PIRQ%c: %d\n", 'A' + i, pirq[i]); |
| 111 | } |
| 112 | |
| 113 | u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) |
| 114 | { |
Bin Meng | 7a01b87 | 2015-04-27 14:16:01 +0800 | [diff] [blame] | 115 | struct irq_routing_table *rom_rt; |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 116 | |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 117 | /* Align the table to be 16 byte aligned */ |
| 118 | addr = ALIGN(addr, 16); |
| 119 | |
| 120 | debug("Copying Interrupt Routing Table to 0x%x\n", addr); |
Simon Glass | aa0ed9d | 2017-01-16 07:03:42 -0700 | [diff] [blame] | 121 | memcpy((void *)(uintptr_t)addr, rt, rt->size); |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 122 | |
Bin Meng | 7a01b87 | 2015-04-27 14:16:01 +0800 | [diff] [blame] | 123 | /* |
| 124 | * We do the sanity check here against the copied table after memcpy, |
| 125 | * as something might go wrong after the memcpy, which is normally |
| 126 | * due to the F segment decode is not turned on to systeam RAM. |
| 127 | */ |
Simon Glass | aa0ed9d | 2017-01-16 07:03:42 -0700 | [diff] [blame] | 128 | rom_rt = (struct irq_routing_table *)(uintptr_t)addr; |
Bin Meng | 7a01b87 | 2015-04-27 14:16:01 +0800 | [diff] [blame] | 129 | if (rom_rt->signature != PIRQ_SIGNATURE || |
| 130 | rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) { |
| 131 | printf("Interrupt Routing Table not valid\n"); |
| 132 | return addr; |
| 133 | } |
| 134 | |
Bin Meng | 45236ad | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 135 | return addr + rt->size; |
| 136 | } |
Simon Glass | 25271ae | 2019-12-06 21:42:15 -0700 | [diff] [blame] | 137 | |
| 138 | ulong write_pirq_routing_table(ulong addr) |
| 139 | { |
| 140 | if (!gd->arch.pirq_routing_table) |
| 141 | return addr; |
| 142 | |
| 143 | return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table); |
| 144 | } |