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git01.mediatek.com / filogic / uboot / 9240876ab0bc948cb01346190f4014eee4d971db / . / board / sunxi / dram_sun4i_auto.c
blob: 7d4409b51e9882ca3707154f4c8f4939f43880af [file] [log] [blame]
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]1#include <common.h>
2#include <asm/arch/dram.h>
3
4static struct dram_para dram_para = {
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]5 .clock = CONFIG_DRAM_CLK,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]6 .type = 3,
7 .rank_num = 1,
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]8 .density = 0,
9 .io_width = 0,
10 .bus_width = 0,
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]11 .zq = CONFIG_DRAM_ZQ,
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200[diff] [blame]12 .odt_en = IS_ENABLED(CONFIG_DRAM_ODT_EN),
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]13 .size = 0,
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame]14#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
15 .cas = 6,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]16 .tpr0 = 0x30926692,
17 .tpr1 = 0x1090,
18 .tpr2 = 0x1a0c8,
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame]19 .emr2 = 0,
20#else
21# include "dram_timings_sun4i.h"
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200[diff] [blame]22 .active_windowing = 1,
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200[diff] [blame]23#endif
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200[diff] [blame]24 .tpr3 = CONFIG_DRAM_TPR3,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]25 .tpr4 = 0,
26 .tpr5 = 0,
Hans de Goede59d9fc72015-01-17 14:24:55 +0100[diff] [blame]27 .emr1 = CONFIG_DRAM_EMR1,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]28 .emr3 = 0,
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200[diff] [blame]29 .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY,
Hans de Goede7f15c692014-07-26 16:51:08 +0200[diff] [blame]30};
31
32unsigned long sunxi_dram_init(void)
33{
34 return dramc_init(&dram_para);
35}