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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek SGMIISYS Controller
8
9maintainers:
10 - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13 The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks
14 to the ethernet subsystem to which it is attached.
15
16properties:
17 compatible:
Tom Rini93743d22024-04-01 09:08:13 -040018 oneOf:
19 - items:
20 - enum:
21 - mediatek,mt7622-sgmiisys
22 - mediatek,mt7629-sgmiisys
23 - mediatek,mt7981-sgmiisys_0
24 - mediatek,mt7981-sgmiisys_1
25 - mediatek,mt7986-sgmiisys_0
26 - mediatek,mt7986-sgmiisys_1
27 - const: syscon
28 - items:
29 - enum:
30 - mediatek,mt7988-sgmiisys0
31 - mediatek,mt7988-sgmiisys1
32 - const: simple-mfd
33 - const: syscon
Tom Rini53633a82024-02-29 12:33:36 -050034
35 reg:
36 maxItems: 1
37
38 '#clock-cells':
39 const: 1
40
41 mediatek,pnswap:
42 description: Invert polarity of the SGMII data lanes
43 type: boolean
44
Tom Rini93743d22024-04-01 09:08:13 -040045 pcs:
46 type: object
47 description: MediaTek LynxI HSGMII PCS
48 properties:
49 compatible:
50 const: mediatek,mt7988-sgmii
51
52 clocks:
53 maxItems: 3
54
55 clock-names:
56 items:
57 - const: sgmii_sel
58 - const: sgmii_tx
59 - const: sgmii_rx
60
61 required:
62 - compatible
63 - clocks
64 - clock-names
65
66 additionalProperties: false
67
Tom Rini53633a82024-02-29 12:33:36 -050068required:
69 - compatible
70 - reg
71 - '#clock-cells'
72
Tom Rini93743d22024-04-01 09:08:13 -040073allOf:
74 - if:
75 properties:
76 compatible:
77 contains:
78 enum:
79 - mediatek,mt7988-sgmiisys0
80 - mediatek,mt7988-sgmiisys1
81
82 then:
83 required:
84 - pcs
85
86 else:
87 properties:
88 pcs: false
89
Tom Rini53633a82024-02-29 12:33:36 -050090additionalProperties: false
91
92examples:
93 - |
94 soc {
95 #address-cells = <2>;
96 #size-cells = <2>;
97 sgmiisys: syscon@1b128000 {
98 compatible = "mediatek,mt7622-sgmiisys", "syscon";
99 reg = <0 0x1b128000 0 0x1000>;
100 #clock-cells = <1>;
101 };
102 };