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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip KSZ Series Ethernet switches
8
9maintainers:
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
12
13allOf:
Tom Rini53633a82024-02-29 12:33:36 -050014 - $ref: /schemas/spi/spi-peripheral-props.yaml#
15
16properties:
17 # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
18 # required and optional properties.
19 compatible:
20 enum:
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
25 - microchip,ksz8873
26 - microchip,ksz9477
27 - microchip,ksz9897
28 - microchip,ksz9896
29 - microchip,ksz9567
30 - microchip,ksz8565
31 - microchip,ksz9893
32 - microchip,ksz9563
33 - microchip,ksz8563
34
35 reset-gpios:
36 description:
37 Should be a gpio specifier for a reset line.
38 maxItems: 1
39
40 wakeup-source: true
41
42 microchip,synclko-125:
43 $ref: /schemas/types.yaml#/definitions/flag
44 description:
45 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
46
47 microchip,synclko-disable:
48 $ref: /schemas/types.yaml#/definitions/flag
49 description:
50 Set if the output SYNCLKO clock should be disabled. Do not mix with
51 microchip,synclko-125.
52
53 microchip,io-drive-strength-microamp:
54 description:
55 IO Pad Drive Strength
56 enum: [8000, 16000]
57 default: 16000
58
59 microchip,hi-drive-strength-microamp:
60 description:
61 High Speed Drive Strength. Controls drive strength of GMII / RGMII /
62 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
63 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
64 default: 24000
65
66 microchip,lo-drive-strength-microamp:
67 description:
68 Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
69 COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
70 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
71 default: 8000
72
73 interrupts:
74 maxItems: 1
75
76required:
77 - compatible
78 - reg
79
Tom Rini93743d22024-04-01 09:08:13 -040080if:
81 not:
82 properties:
83 compatible:
84 enum:
85 - microchip,ksz8863
86 - microchip,ksz8873
87then:
88 $ref: dsa.yaml#/$defs/ethernet-ports
89else:
90 patternProperties:
91 "^(ethernet-)?ports$":
92 patternProperties:
93 "^(ethernet-)?port@[0-2]$":
94 $ref: dsa-port.yaml#
95 unevaluatedProperties: false
96 properties:
97 microchip,rmii-clk-internal:
98 $ref: /schemas/types.yaml#/definitions/flag
99 description:
100 When ksz88x3 is acting as clock provier (via REFCLKO) it
101 can select between internal and external RMII reference
102 clock. Internal reference clock means that the clock for
103 the RMII of ksz88x3 is provided by the ksz88x3 internally
104 and the REFCLKI pin is unconnected. For the external
105 reference clock, the clock needs to be fed back to ksz88x3
106 via REFCLKI.
107 If microchip,rmii-clk-internal is set, ksz88x3 will provide
108 rmii reference clock internally, otherwise reference clock
109 should be provided externally.
110 dependencies:
111 microchip,rmii-clk-internal: [ethernet]
112
Tom Rini53633a82024-02-29 12:33:36 -0500113unevaluatedProperties: false
114
115examples:
116 - |
117 #include <dt-bindings/gpio/gpio.h>
118
119 // Ethernet switch connected via SPI to the host, CPU port wired to eth0:
120 eth0 {
121 fixed-link {
122 speed = <1000>;
123 full-duplex;
124 };
125 };
126
127 spi {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 pinctrl-0 = <&pinctrl_spi_ksz>;
132 cs-gpios = <&pioC 25 0>;
133 id = <1>;
134
135 ksz9477: switch@0 {
136 compatible = "microchip,ksz9477";
137 reg = <0>;
138 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
139
140 spi-max-frequency = <44000000>;
141
142 ethernet-ports {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 port@0 {
146 reg = <0>;
147 label = "lan1";
148 };
149 port@1 {
150 reg = <1>;
151 label = "lan2";
152 };
153 port@2 {
154 reg = <2>;
155 label = "lan3";
156 };
157 port@3 {
158 reg = <3>;
159 label = "lan4";
160 };
161 port@4 {
162 reg = <4>;
163 label = "lan5";
164 };
165 port@5 {
166 reg = <5>;
167 ethernet = <&eth0>;
168 phy-mode = "rgmii";
169
170 fixed-link {
171 speed = <1000>;
172 full-duplex;
173 };
174 };
175 };
176 };
177
178 ksz8565: switch@1 {
179 compatible = "microchip,ksz8565";
180 reg = <1>;
181
182 spi-max-frequency = <44000000>;
183
184 ethernet-ports {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 port@0 {
188 reg = <0>;
189 label = "lan1";
190 };
191 port@1 {
192 reg = <1>;
193 label = "lan2";
194 };
195 port@2 {
196 reg = <2>;
197 label = "lan3";
198 };
199 port@3 {
200 reg = <3>;
201 label = "lan4";
202 };
203 port@6 {
204 reg = <6>;
205 ethernet = <&eth0>;
206 phy-mode = "rgmii";
207
208 fixed-link {
209 speed = <1000>;
210 full-duplex;
211 };
212 };
213 };
214 };
215 };
216...