Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * cpu/ppc4xx/40x_spd_sdram.c |
| 3 | * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a |
| 4 | * SDRAM controller. Those are all current 405 PPC's. |
| 5 | * |
| 6 | * (C) Copyright 2001 |
| 7 | * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com |
| 8 | * |
| 9 | * Based on code by: |
| 10 | * |
| 11 | * Kenneth Johansson ,Ericsson AB. |
| 12 | * kenneth.johansson@etx.ericsson.se |
| 13 | * |
| 14 | * hacked up by bill hunter. fixed so we could run before |
| 15 | * serial_init and console_init. previous version avoided this by |
| 16 | * running out of cache memory during serial/console init, then running |
| 17 | * this code later. |
| 18 | * |
| 19 | * (C) Copyright 2002 |
| 20 | * Jun Gu, Artesyn Technology, jung@artesyncp.com |
| 21 | * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. |
| 22 | * |
| 23 | * (C) Copyright 2005 |
| 24 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 25 | * |
| 26 | * See file CREDITS for list of people who contributed to this |
| 27 | * project. |
| 28 | * |
| 29 | * This program is free software; you can redistribute it and/or |
| 30 | * modify it under the terms of the GNU General Public License as |
| 31 | * published by the Free Software Foundation; either version 2 of |
| 32 | * the License, or (at your option) any later version. |
| 33 | * |
| 34 | * This program is distributed in the hope that it will be useful, |
| 35 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 36 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 37 | * GNU General Public License for more details. |
| 38 | * |
| 39 | * You should have received a copy of the GNU General Public License |
| 40 | * along with this program; if not, write to the Free Software |
| 41 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 42 | * MA 02111-1307 USA |
| 43 | */ |
| 44 | |
| 45 | #include <common.h> |
| 46 | #include <asm/processor.h> |
| 47 | #include <i2c.h> |
| 48 | #include <ppc4xx.h> |
| 49 | |
| 50 | #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440) |
| 51 | |
| 52 | /* |
| 53 | * Set default values |
| 54 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #ifndef CONFIG_SYS_I2C_SPEED |
| 56 | #define CONFIG_SYS_I2C_SPEED 50000 |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 57 | #endif |
| 58 | |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 59 | #define ONE_BILLION 1000000000 |
| 60 | |
| 61 | #define SDRAM0_CFG_DCE 0x80000000 |
| 62 | #define SDRAM0_CFG_SRE 0x40000000 |
| 63 | #define SDRAM0_CFG_PME 0x20000000 |
| 64 | #define SDRAM0_CFG_MEMCHK 0x10000000 |
| 65 | #define SDRAM0_CFG_REGEN 0x08000000 |
| 66 | #define SDRAM0_CFG_ECCDD 0x00400000 |
| 67 | #define SDRAM0_CFG_EMDULR 0x00200000 |
| 68 | #define SDRAM0_CFG_DRW_SHIFT (31-6) |
| 69 | #define SDRAM0_CFG_BRPF_SHIFT (31-8) |
| 70 | |
| 71 | #define SDRAM0_TR_CASL_SHIFT (31-8) |
| 72 | #define SDRAM0_TR_PTA_SHIFT (31-13) |
| 73 | #define SDRAM0_TR_CTP_SHIFT (31-15) |
| 74 | #define SDRAM0_TR_LDF_SHIFT (31-17) |
| 75 | #define SDRAM0_TR_RFTA_SHIFT (31-29) |
| 76 | #define SDRAM0_TR_RCD_SHIFT (31-31) |
| 77 | |
| 78 | #define SDRAM0_RTR_SHIFT (31-15) |
| 79 | #define SDRAM0_ECCCFG_SHIFT (31-11) |
| 80 | |
| 81 | /* SDRAM0_CFG enable macro */ |
| 82 | #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) |
| 83 | |
| 84 | #define SDRAM0_BXCR_SZ_MASK 0x000e0000 |
| 85 | #define SDRAM0_BXCR_AM_MASK 0x0000e000 |
| 86 | |
| 87 | #define SDRAM0_BXCR_SZ_SHIFT (31-14) |
| 88 | #define SDRAM0_BXCR_AM_SHIFT (31-18) |
| 89 | |
| 90 | #define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) |
| 91 | #define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) |
| 92 | |
| 93 | #ifdef CONFIG_SPDDRAM_SILENT |
| 94 | # define SPD_ERR(x) do { return 0; } while (0) |
| 95 | #else |
| 96 | # define SPD_ERR(x) do { printf(x); return(0); } while (0) |
| 97 | #endif |
| 98 | |
| 99 | #define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) |
| 100 | |
| 101 | /* function prototypes */ |
| 102 | int spd_read(uint addr); |
| 103 | |
| 104 | |
| 105 | /* |
| 106 | * This function is reading data from the DIMM module EEPROM over the SPD bus |
| 107 | * and uses that to program the sdram controller. |
| 108 | * |
| 109 | * This works on boards that has the same schematics that the AMCC walnut has. |
| 110 | * |
| 111 | * Input: null for default I2C spd functions or a pointer to a custom function |
| 112 | * returning spd_data. |
| 113 | */ |
| 114 | |
| 115 | long int spd_sdram(int(read_spd)(uint addr)) |
| 116 | { |
| 117 | int tmp,row,col; |
| 118 | int total_size,bank_size,bank_code; |
| 119 | int ecc_on; |
| 120 | int mode; |
| 121 | int bank_cnt; |
| 122 | |
| 123 | int sdram0_pmit=0x07c00000; |
| 124 | #ifndef CONFIG_405EP /* not on PPC405EP */ |
Wolfgang Denk | dc770c7 | 2008-07-14 15:19:07 +0200 | [diff] [blame] | 125 | int sdram0_besr0 = -1; |
| 126 | int sdram0_besr1 = -1; |
| 127 | int sdram0_eccesr = -1; |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 128 | #endif |
| 129 | int sdram0_ecccfg; |
| 130 | |
| 131 | int sdram0_rtr=0; |
| 132 | int sdram0_tr=0; |
| 133 | |
| 134 | int sdram0_b0cr; |
| 135 | int sdram0_b1cr; |
| 136 | int sdram0_b2cr; |
| 137 | int sdram0_b3cr; |
| 138 | |
| 139 | int sdram0_cfg=0; |
| 140 | |
| 141 | int t_rp; |
| 142 | int t_rcd; |
| 143 | int t_ras; |
| 144 | int t_rc; |
| 145 | int min_cas; |
| 146 | |
Stefan Roese | edd73f2 | 2007-10-21 08:12:41 +0200 | [diff] [blame] | 147 | PPC4xx_SYS_INFO sys_info; |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 148 | unsigned long bus_period_x_10; |
| 149 | |
| 150 | /* |
| 151 | * get the board info |
| 152 | */ |
| 153 | get_sys_info(&sys_info); |
| 154 | bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); |
| 155 | |
| 156 | if (read_spd == 0){ |
| 157 | read_spd=spd_read; |
| 158 | /* |
| 159 | * Make sure I2C controller is initialized |
| 160 | * before continuing. |
| 161 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | /* Make shure we are using SDRAM */ |
| 166 | if (read_spd(2) != 0x04) { |
| 167 | SPD_ERR("SDRAM - non SDRAM memory module found\n"); |
| 168 | } |
| 169 | |
| 170 | /* ------------------------------------------------------------------ |
| 171 | * configure memory timing register |
| 172 | * |
| 173 | * data from DIMM: |
| 174 | * 27 IN Row Precharge Time ( t RP) |
| 175 | * 29 MIN RAS to CAS Delay ( t RCD) |
| 176 | * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS |
| 177 | * -------------------------------------------------------------------*/ |
| 178 | |
| 179 | /* |
| 180 | * first figure out which cas latency mode to use |
| 181 | * use the min supported mode |
| 182 | */ |
| 183 | |
| 184 | tmp = read_spd(127) & 0x6; |
| 185 | if (tmp == 0x02) { /* only cas = 2 supported */ |
| 186 | min_cas = 2; |
| 187 | /* t_ck = read_spd(9); */ |
| 188 | /* t_ac = read_spd(10); */ |
| 189 | } else if (tmp == 0x04) { /* only cas = 3 supported */ |
| 190 | min_cas = 3; |
| 191 | /* t_ck = read_spd(9); */ |
| 192 | /* t_ac = read_spd(10); */ |
| 193 | } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ |
| 194 | min_cas = 2; |
| 195 | /* t_ck = read_spd(23); */ |
| 196 | /* t_ac = read_spd(24); */ |
| 197 | } else { |
| 198 | SPD_ERR("SDRAM - unsupported CAS latency \n"); |
| 199 | } |
| 200 | |
| 201 | /* get some timing values, t_rp,t_rcd,t_ras,t_rc |
| 202 | */ |
| 203 | t_rp = read_spd(27); |
| 204 | t_rcd = read_spd(29); |
| 205 | t_ras = read_spd(30); |
| 206 | t_rc = t_ras + t_rp; |
| 207 | |
| 208 | /* The following timing calcs subtract 1 before deviding. |
| 209 | * this has effect of using ceiling instead of floor rounding, |
| 210 | * and also subtracting 1 to convert number to reg value |
| 211 | */ |
| 212 | /* set up CASL */ |
| 213 | sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; |
| 214 | /* set up PTA */ |
| 215 | sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; |
| 216 | /* set up CTP */ |
| 217 | tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; |
| 218 | if (tmp < 1) |
| 219 | tmp = 1; |
| 220 | sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; |
| 221 | /* set LDF = 2 cycles, reg value = 1 */ |
| 222 | sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; |
| 223 | /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ |
| 224 | tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; |
| 225 | if (tmp < 0) |
| 226 | tmp = 0; |
| 227 | if (tmp > 6) |
| 228 | tmp = 6; |
| 229 | sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; |
| 230 | /* set RCD = t_rcd/bus_period*/ |
| 231 | sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; |
| 232 | |
| 233 | |
| 234 | /*------------------------------------------------------------------ |
| 235 | * configure RTR register |
| 236 | * -------------------------------------------------------------------*/ |
| 237 | row = read_spd(3); |
| 238 | col = read_spd(4); |
| 239 | tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ |
| 240 | switch (tmp) { |
| 241 | case 0x00: |
| 242 | tmp = 15625; |
| 243 | break; |
| 244 | case 0x01: |
| 245 | tmp = 15625 / 4; |
| 246 | break; |
| 247 | case 0x02: |
| 248 | tmp = 15625 / 2; |
| 249 | break; |
| 250 | case 0x03: |
| 251 | tmp = 15625 * 2; |
| 252 | break; |
| 253 | case 0x04: |
| 254 | tmp = 15625 * 4; |
| 255 | break; |
| 256 | case 0x05: |
| 257 | tmp = 15625 * 8; |
| 258 | break; |
| 259 | default: |
| 260 | SPD_ERR("SDRAM - Bad refresh period \n"); |
| 261 | } |
| 262 | /* convert from nsec to bus cycles */ |
| 263 | tmp = (tmp * 10) / bus_period_x_10; |
| 264 | sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; |
| 265 | |
| 266 | /*------------------------------------------------------------------ |
| 267 | * determine the number of banks used |
| 268 | * -------------------------------------------------------------------*/ |
| 269 | /* byte 7:6 is module data width */ |
| 270 | if (read_spd(7) != 0) |
| 271 | SPD_ERR("SDRAM - unsupported module width\n"); |
| 272 | tmp = read_spd(6); |
| 273 | if (tmp < 32) |
| 274 | SPD_ERR("SDRAM - unsupported module width\n"); |
| 275 | else if (tmp < 64) |
| 276 | bank_cnt = 1; /* one bank per sdram side */ |
| 277 | else if (tmp < 73) |
| 278 | bank_cnt = 2; /* need two banks per side */ |
| 279 | else if (tmp < 161) |
| 280 | bank_cnt = 4; /* need four banks per side */ |
| 281 | else |
| 282 | SPD_ERR("SDRAM - unsupported module width\n"); |
| 283 | |
| 284 | /* byte 5 is the module row count (refered to as dimm "sides") */ |
| 285 | tmp = read_spd(5); |
| 286 | if (tmp == 1) |
| 287 | ; |
| 288 | else if (tmp==2) |
| 289 | bank_cnt *= 2; |
| 290 | else if (tmp==4) |
| 291 | bank_cnt *= 4; |
| 292 | else |
| 293 | bank_cnt = 8; /* 8 is an error code */ |
| 294 | |
| 295 | if (bank_cnt > 4) /* we only have 4 banks to work with */ |
| 296 | SPD_ERR("SDRAM - unsupported module rows for this width\n"); |
| 297 | |
| 298 | /* now check for ECC ability of module. We only support ECC |
| 299 | * on 32 bit wide devices with 8 bit ECC. |
| 300 | */ |
| 301 | if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { |
| 302 | sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; |
| 303 | ecc_on = 1; |
| 304 | } else { |
| 305 | sdram0_ecccfg = 0; |
| 306 | ecc_on = 0; |
| 307 | } |
| 308 | |
| 309 | /*------------------------------------------------------------------ |
| 310 | * calculate total size |
| 311 | * -------------------------------------------------------------------*/ |
| 312 | /* calculate total size and do sanity check */ |
| 313 | tmp = read_spd(31); |
| 314 | total_size = 1 << 22; /* total_size = 4MB */ |
| 315 | /* now multiply 4M by the smallest device row density */ |
| 316 | /* note that we don't support asymetric rows */ |
| 317 | while (((tmp & 0x0001) == 0) && (tmp != 0)) { |
| 318 | total_size = total_size << 1; |
| 319 | tmp = tmp >> 1; |
| 320 | } |
| 321 | total_size *= read_spd(5); /* mult by module rows (dimm sides) */ |
| 322 | |
| 323 | /*------------------------------------------------------------------ |
| 324 | * map rows * cols * banks to a mode |
| 325 | * -------------------------------------------------------------------*/ |
| 326 | |
| 327 | switch (row) { |
| 328 | case 11: |
| 329 | switch (col) { |
| 330 | case 8: |
| 331 | mode=4; /* mode 5 */ |
| 332 | break; |
| 333 | case 9: |
| 334 | case 10: |
| 335 | mode=0; /* mode 1 */ |
| 336 | break; |
| 337 | default: |
| 338 | SPD_ERR("SDRAM - unsupported mode\n"); |
| 339 | } |
| 340 | break; |
| 341 | case 12: |
| 342 | switch (col) { |
| 343 | case 8: |
| 344 | mode=3; /* mode 4 */ |
| 345 | break; |
| 346 | case 9: |
| 347 | case 10: |
| 348 | mode=1; /* mode 2 */ |
| 349 | break; |
| 350 | default: |
| 351 | SPD_ERR("SDRAM - unsupported mode\n"); |
| 352 | } |
| 353 | break; |
| 354 | case 13: |
| 355 | switch (col) { |
| 356 | case 8: |
| 357 | mode=5; /* mode 6 */ |
| 358 | break; |
| 359 | case 9: |
| 360 | case 10: |
| 361 | if (read_spd(17) == 2) |
| 362 | mode = 6; /* mode 7 */ |
| 363 | else |
| 364 | mode = 2; /* mode 3 */ |
| 365 | break; |
| 366 | case 11: |
| 367 | mode = 2; /* mode 3 */ |
| 368 | break; |
| 369 | default: |
| 370 | SPD_ERR("SDRAM - unsupported mode\n"); |
| 371 | } |
| 372 | break; |
| 373 | default: |
| 374 | SPD_ERR("SDRAM - unsupported mode\n"); |
| 375 | } |
| 376 | |
| 377 | /*------------------------------------------------------------------ |
| 378 | * using the calculated values, compute the bank |
| 379 | * config register values. |
| 380 | * -------------------------------------------------------------------*/ |
| 381 | sdram0_b1cr = 0; |
| 382 | sdram0_b2cr = 0; |
| 383 | sdram0_b3cr = 0; |
| 384 | |
| 385 | /* compute the size of each bank */ |
| 386 | bank_size = total_size / bank_cnt; |
| 387 | /* convert bank size to bank size code for ppc4xx |
| 388 | by takeing log2(bank_size) - 22 */ |
| 389 | tmp = bank_size; /* start with tmp = bank_size */ |
| 390 | bank_code = 0; /* and bank_code = 0 */ |
| 391 | while (tmp > 1) { /* this takes log2 of tmp */ |
| 392 | bank_code++; /* and stores result in bank_code */ |
| 393 | tmp = tmp >> 1; |
| 394 | } /* bank_code is now log2(bank_size) */ |
| 395 | bank_code -= 22; /* subtract 22 to get the code */ |
| 396 | |
| 397 | tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; |
| 398 | sdram0_b0cr = (bank_size * 0) | tmp; |
| 399 | #ifndef CONFIG_405EP /* not on PPC405EP */ |
| 400 | if (bank_cnt > 1) |
| 401 | sdram0_b2cr = (bank_size * 1) | tmp; |
| 402 | if (bank_cnt > 2) |
| 403 | sdram0_b1cr = (bank_size * 2) | tmp; |
| 404 | if (bank_cnt > 3) |
| 405 | sdram0_b3cr = (bank_size * 3) | tmp; |
| 406 | #else |
| 407 | /* PPC405EP chip only supports two SDRAM banks */ |
| 408 | if (bank_cnt > 1) |
| 409 | sdram0_b1cr = (bank_size * 1) | tmp; |
| 410 | if (bank_cnt > 2) |
| 411 | total_size = 2 * bank_size; |
| 412 | #endif |
| 413 | |
| 414 | /* |
| 415 | * enable sdram controller DCE=1 |
| 416 | * enable burst read prefetch to 32 bytes BRPF=2 |
| 417 | * leave other functions off |
| 418 | */ |
| 419 | |
| 420 | /*------------------------------------------------------------------ |
| 421 | * now that we've done our calculations, we are ready to |
| 422 | * program all the registers. |
| 423 | * -------------------------------------------------------------------*/ |
| 424 | |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 425 | /* disable memcontroller so updates work */ |
Stefan Roese | 8f9cdda | 2009-09-24 14:10:30 +0200 | [diff] [blame] | 426 | mtsdram(SDRAM0_CFG, 0); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 427 | |
| 428 | #ifndef CONFIG_405EP /* not on PPC405EP */ |
Stefan Roese | 8f9cdda | 2009-09-24 14:10:30 +0200 | [diff] [blame] | 429 | mtsdram(SDRAM0_BESR0, sdram0_besr0); |
| 430 | mtsdram(SDRAM0_BESR1, sdram0_besr1); |
| 431 | mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg); |
| 432 | mtsdram(SDRAM0_ECCESR, sdram0_eccesr); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 433 | #endif |
Stefan Roese | 8f9cdda | 2009-09-24 14:10:30 +0200 | [diff] [blame] | 434 | mtsdram(SDRAM0_RTR, sdram0_rtr); |
| 435 | mtsdram(SDRAM0_PMIT, sdram0_pmit); |
| 436 | mtsdram(SDRAM0_B0CR, sdram0_b0cr); |
| 437 | mtsdram(SDRAM0_B1CR, sdram0_b1cr); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 438 | #ifndef CONFIG_405EP /* not on PPC405EP */ |
Stefan Roese | 8f9cdda | 2009-09-24 14:10:30 +0200 | [diff] [blame] | 439 | mtsdram(SDRAM0_B2CR, sdram0_b2cr); |
| 440 | mtsdram(SDRAM0_B3CR, sdram0_b3cr); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 441 | #endif |
Stefan Roese | 8f9cdda | 2009-09-24 14:10:30 +0200 | [diff] [blame] | 442 | mtsdram(SDRAM0_TR, sdram0_tr); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 443 | |
| 444 | /* SDRAM have a power on delay, 500 micro should do */ |
| 445 | udelay(500); |
| 446 | sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; |
| 447 | if (ecc_on) |
| 448 | sdram0_cfg |= SDRAM0_CFG_MEMCHK; |
Stefan Roese | 8f9cdda | 2009-09-24 14:10:30 +0200 | [diff] [blame] | 449 | mtsdram(SDRAM0_CFG, sdram0_cfg); |
Stefan Roese | c229533 | 2007-02-20 10:35:42 +0100 | [diff] [blame] | 450 | |
| 451 | return (total_size); |
| 452 | } |
| 453 | |
| 454 | int spd_read(uint addr) |
| 455 | { |
| 456 | uchar data[2]; |
| 457 | |
| 458 | if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) |
| 459 | return (int)data[0]; |
| 460 | else |
| 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | #endif /* CONFIG_SPD_EEPROM */ |