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git01.mediatek.com / filogic / uboot / 91db793c430eb10c1a0dd41a25a5da1a26dfcd80 / . / arch / arm / dts / imx8mm-venice-gw7902.dts
blob: b0404ec4c8af3562ab0ede7d8fc66f6477883ee3 [file] [log] [blame]
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7902 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
18
19 aliases {
20 usb0 = &usbotg1;
21 usb1 = &usbotg2;
22 };
23
24 chosen {
25 stdout-path = &uart2;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x80000000>;
31 };
32
33 can20m: can20m {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <20000000>;
37 clock-output-names = "can20m";
38 };
39
40 gpio-keys {
41 compatible = "gpio-keys";
42
43 user-pb {
44 label = "user_pb";
45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
46 linux,code = <BTN_0>;
47 };
48
49 user-pb1x {
50 label = "user_pb1x";
51 linux,code = <BTN_1>;
52 interrupt-parent = <&gsc>;
53 interrupts = <0>;
54 };
55
56 key-erased {
57 label = "key_erased";
58 linux,code = <BTN_2>;
59 interrupt-parent = <&gsc>;
60 interrupts = <1>;
61 };
62
63 eeprom-wp {
64 label = "eeprom_wp";
65 linux,code = <BTN_3>;
66 interrupt-parent = <&gsc>;
67 interrupts = <2>;
68 };
69
70 tamper {
71 label = "tamper";
72 linux,code = <BTN_4>;
73 interrupt-parent = <&gsc>;
74 interrupts = <5>;
75 };
76
77 switch-hold {
78 label = "switch_hold";
79 linux,code = <BTN_5>;
80 interrupt-parent = <&gsc>;
81 interrupts = <7>;
82 };
83 };
84
85 led-controller {
86 compatible = "gpio-leds";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_gpio_leds>;
89
90 led-0 {
91 function = LED_FUNCTION_STATUS;
92 color = <LED_COLOR_ID_GREEN>;
93 label = "panel1";
94 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
95 default-state = "off";
96 };
97
98 led-1 {
99 function = LED_FUNCTION_STATUS;
100 color = <LED_COLOR_ID_GREEN>;
101 label = "panel2";
102 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
103 default-state = "off";
104 };
105
106 led-2 {
107 function = LED_FUNCTION_STATUS;
108 color = <LED_COLOR_ID_GREEN>;
109 label = "panel3";
110 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
111 default-state = "off";
112 };
113
114 led-3 {
115 function = LED_FUNCTION_STATUS;
116 color = <LED_COLOR_ID_GREEN>;
117 label = "panel4";
118 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
119 default-state = "off";
120 };
121
122 led-4 {
123 function = LED_FUNCTION_STATUS;
124 color = <LED_COLOR_ID_GREEN>;
125 label = "panel5";
126 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
127 default-state = "off";
128 };
129 };
130
131 pps {
132 compatible = "pps-gpio";
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_pps>;
135 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
136 status = "okay";
137 };
138
139 reg_3p3v: regulator-3p3v {
140 compatible = "regulator-fixed";
141 regulator-name = "3P3V";
142 regulator-min-microvolt = <3300000>;
143 regulator-max-microvolt = <3300000>;
144 };
145
146 reg_usb1_vbus: regulator-usb1 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb1>;
149 compatible = "regulator-fixed";
150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high;
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
155 };
156
157 reg_wifi: regulator-wifi {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_reg_wl>;
160 compatible = "regulator-fixed";
161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high;
164 startup-delay-us = <100>;
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 };
168};
169
170&A53_0 {
171 cpu-supply = <&buck2>;
172};
173
174&A53_1 {
175 cpu-supply = <&buck2>;
176};
177
178&A53_2 {
179 cpu-supply = <&buck2>;
180};
181
182&A53_3 {
183 cpu-supply = <&buck2>;
184};
185
186&ddrc {
187 operating-points-v2 = <&ddrc_opp_table>;
188
189 ddrc_opp_table: opp-table {
190 compatible = "operating-points-v2";
191
192 opp-25M {
193 opp-hz = /bits/ 64 <25000000>;
194 };
195
196 opp-100M {
197 opp-hz = /bits/ 64 <100000000>;
198 };
199
200 opp-750M {
201 opp-hz = /bits/ 64 <750000000>;
202 };
203 };
204};
205
206&ecspi1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay";
211
212 can@0 {
213 compatible = "microchip,mcp2515";
214 reg = <0>;
215 clocks = <&can20m>;
216 oscillator-frequency = <20000000>;
217 interrupt-parent = <&gpio2>;
218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
219 spi-max-frequency = <10000000>;
220 };
221};
222
223/* off-board header */
224&ecspi2 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_spi2>;
227 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
228 status = "okay";
229};
230
231&fec1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_fec1>;
234 phy-mode = "rgmii-id";
235 phy-handle = <&ethphy0>;
236 local-mac-address = [00 00 00 00 00 00];
237 status = "okay";
238
239 mdio {
240 #address-cells = <1>;
241 #size-cells = <0>;
242
243 ethphy0: ethernet-phy@0 {
244 compatible = "ethernet-phy-ieee802.3-c22";
245 reg = <0>;
Tim Harvey3c436182022-04-13 09:09:49 -0700[diff] [blame]246 /* TI DP83867 props */
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]247 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
248 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
249 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
250 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
Tim Harvey3c436182022-04-13 09:09:49 -0700[diff] [blame]251 /* GPY111 props */
252 rx-internal-delay-ps = <2000>;
253 tx-internal-delay-ps = <2500>;
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]254 };
255 };
256};
257
258&i2c1 {
259 clock-frequency = <100000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_i2c1>;
262 status = "okay";
263
264 gsc: gsc@20 {
265 compatible = "gw,gsc";
266 reg = <0x20>;
267 pinctrl-0 = <&pinctrl_gsc>;
268 interrupt-parent = <&gpio2>;
269 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
270 interrupt-controller;
271 #interrupt-cells = <1>;
272
273 adc {
274 compatible = "gw,gsc-adc";
275 #address-cells = <1>;
276 #size-cells = <0>;
277
278 channel@6 {
279 gw,mode = <0>;
280 reg = <0x06>;
281 label = "temp";
282 };
283
284 channel@8 {
285 gw,mode = <1>;
286 reg = <0x08>;
287 label = "vdd_bat";
288 };
289
290 channel@82 {
291 gw,mode = <2>;
292 reg = <0x82>;
293 label = "vin";
294 gw,voltage-divider-ohms = <22100 1000>;
295 gw,voltage-offset-microvolt = <700000>;
296 };
297
298 channel@84 {
299 gw,mode = <2>;
300 reg = <0x84>;
301 label = "vin_4p0";
302 gw,voltage-divider-ohms = <10000 10000>;
303 };
304
305 channel@86 {
306 gw,mode = <2>;
307 reg = <0x86>;
308 label = "vdd_3p3";
309 gw,voltage-divider-ohms = <10000 10000>;
310 };
311
312 channel@88 {
313 gw,mode = <2>;
314 reg = <0x88>;
315 label = "vdd_0p9";
316 };
317
318 channel@8c {
319 gw,mode = <2>;
320 reg = <0x8c>;
321 label = "vdd_soc";
322 };
323
324 channel@8e {
325 gw,mode = <2>;
326 reg = <0x8e>;
327 label = "vdd_arm";
328 };
329
330 channel@90 {
331 gw,mode = <2>;
332 reg = <0x90>;
333 label = "vdd_1p8";
334 };
335
336 channel@92 {
337 gw,mode = <2>;
338 reg = <0x92>;
339 label = "vdd_dram";
340 };
341
342 channel@98 {
343 gw,mode = <2>;
344 reg = <0x98>;
345 label = "vdd_1p0";
346 };
347
348 channel@9a {
349 gw,mode = <2>;
350 reg = <0x9a>;
351 label = "vdd_2p5";
352 gw,voltage-divider-ohms = <10000 10000>;
353 };
354
Tim Harveyf6d4bc42022-03-08 10:44:43 -0800[diff] [blame]355 channel@9c {
356 gw,mode = <2>;
357 reg = <0x9c>;
358 label = "vdd_5p0";
359 gw,voltage-divider-ohms = <10000 10000>;
360 };
361
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]362 channel@a2 {
363 gw,mode = <2>;
364 reg = <0xa2>;
365 label = "vdd_gsc";
366 gw,voltage-divider-ohms = <10000 10000>;
367 };
368 };
369 };
370
371 gpio: gpio@23 {
372 compatible = "nxp,pca9555";
373 reg = <0x23>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-parent = <&gsc>;
377 interrupts = <4>;
378 };
379
380 pmic@4b {
381 compatible = "rohm,bd71847";
382 reg = <0x4b>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_pmic>;
385 interrupt-parent = <&gpio3>;
386 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
387 rohm,reset-snvs-powered;
388 #clock-cells = <0>;
389 clocks = <&osc_32k 0>;
390 clock-output-names = "clk-32k-out";
391
392 regulators {
393 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
394 BUCK1 {
395 regulator-name = "buck1";
396 regulator-min-microvolt = <700000>;
397 regulator-max-microvolt = <1300000>;
398 regulator-boot-on;
399 regulator-always-on;
400 regulator-ramp-delay = <1250>;
401 };
402
403 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
404 buck2: BUCK2 {
405 regulator-name = "buck2";
406 regulator-min-microvolt = <700000>;
407 regulator-max-microvolt = <1300000>;
408 regulator-boot-on;
409 regulator-always-on;
410 regulator-ramp-delay = <1250>;
411 rohm,dvs-run-voltage = <1000000>;
412 rohm,dvs-idle-voltage = <900000>;
413 };
414
415 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
416 BUCK3 {
417 regulator-name = "buck3";
418 regulator-min-microvolt = <700000>;
419 regulator-max-microvolt = <1350000>;
420 regulator-boot-on;
421 regulator-always-on;
422 };
423
424 /* vdd_3p3 */
425 BUCK4 {
426 regulator-name = "buck4";
427 regulator-min-microvolt = <3000000>;
428 regulator-max-microvolt = <3300000>;
429 regulator-boot-on;
430 regulator-always-on;
431 };
432
433 /* vdd_1p8 */
434 BUCK5 {
435 regulator-name = "buck5";
436 regulator-min-microvolt = <1605000>;
437 regulator-max-microvolt = <1995000>;
438 regulator-boot-on;
439 regulator-always-on;
440 };
441
442 /* vdd_dram */
443 BUCK6 {
444 regulator-name = "buck6";
445 regulator-min-microvolt = <800000>;
446 regulator-max-microvolt = <1400000>;
447 regulator-boot-on;
448 regulator-always-on;
449 };
450
451 /* nvcc_snvs_1p8 */
452 LDO1 {
453 regulator-name = "ldo1";
454 regulator-min-microvolt = <1600000>;
455 regulator-max-microvolt = <1900000>;
456 regulator-boot-on;
457 regulator-always-on;
458 };
459
460 /* vdd_snvs_0p8 */
461 LDO2 {
462 regulator-name = "ldo2";
463 regulator-min-microvolt = <800000>;
464 regulator-max-microvolt = <900000>;
465 regulator-boot-on;
466 regulator-always-on;
467 };
468
469 /* vdda_1p8 */
470 LDO3 {
471 regulator-name = "ldo3";
472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <3300000>;
474 regulator-boot-on;
475 regulator-always-on;
476 };
477
478 LDO4 {
479 regulator-name = "ldo4";
480 regulator-min-microvolt = <900000>;
481 regulator-max-microvolt = <1800000>;
482 regulator-boot-on;
483 regulator-always-on;
484 };
485
486 LDO6 {
487 regulator-name = "ldo6";
488 regulator-min-microvolt = <900000>;
489 regulator-max-microvolt = <1800000>;
490 regulator-boot-on;
491 regulator-always-on;
492 };
493 };
494 };
495
496 eeprom@50 {
497 compatible = "atmel,24c02";
498 reg = <0x50>;
499 pagesize = <16>;
500 };
501
502 eeprom@51 {
503 compatible = "atmel,24c02";
504 reg = <0x51>;
505 pagesize = <16>;
506 };
507
508 eeprom@52 {
509 compatible = "atmel,24c02";
510 reg = <0x52>;
511 pagesize = <16>;
512 };
513
514 eeprom@53 {
515 compatible = "atmel,24c02";
516 reg = <0x53>;
517 pagesize = <16>;
518 };
519
520 rtc@68 {
521 compatible = "dallas,ds1672";
522 reg = <0x68>;
523 };
524};
525
526&i2c2 {
527 clock-frequency = <400000>;
528 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_i2c2>;
530 status = "okay";
531
532 accelerometer@19 {
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_accel>;
535 compatible = "st,lis2de12";
536 reg = <0x19>;
537 st,drdy-int-pin = <1>;
538 interrupt-parent = <&gpio1>;
539 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
540 interrupt-names = "INT1";
541 };
542
543 secure-element@60 {
544 compatible = "nxp,se050";
545 reg = <0x60>;
546 };
547};
548
549/* off-board header */
550&i2c3 {
551 clock-frequency = <400000>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pinctrl_i2c3>;
554 status = "okay";
555};
556
557/* off-board header */
558&i2c4 {
559 clock-frequency = <400000>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pinctrl_i2c4>;
562 status = "okay";
563};
564
565/* off-board header */
566&sai3 {
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_sai3>;
569 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
570 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
571 assigned-clock-rates = <24576000>;
572 status = "okay";
573};
574
575/* RS232/RS485/RS422 selectable */
576&uart1 {
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
579 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
580 cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
581 status = "okay";
582};
583
584/* RS232 console */
585&uart2 {
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_uart2>;
588 status = "okay";
589};
590
591/* bluetooth HCI */
592&uart3 {
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
595 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
596 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
597 status = "okay";
598
599 bluetooth {
600 compatible = "brcm,bcm4330-bt";
601 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
602 };
603};
604
605/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
606&uart4 {
607 pinctrl-names = "default";
608 pinctrl-0 = <&pinctrl_uart4>;
609 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
610 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
611 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
612 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
613 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
614 status = "okay";
615};
616
617&usbotg1 {
618 dr_mode = "host";
619 vbus-supply = <&reg_usb1_vbus>;
620 disable-over-current;
621 status = "okay";
622};
623
624&usbotg2 {
625 dr_mode = "host";
626 disable-over-current;
627 status = "okay";
628};
629
630/* SDIO WiFi */
631&usdhc2 {
632 pinctrl-names = "default";
633 pinctrl-0 = <&pinctrl_usdhc2>;
634 bus-width = <4>;
635 non-removable;
636 vmmc-supply = <&reg_wifi>;
637 status = "okay";
638};
639
640/* eMMC */
641&usdhc3 {
642 pinctrl-names = "default", "state_100mhz", "state_200mhz";
643 pinctrl-0 = <&pinctrl_usdhc3>;
644 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
645 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
646 bus-width = <8>;
647 non-removable;
648 status = "okay";
649};
650
651&wdog1 {
652 pinctrl-names = "default";
653 pinctrl-0 = <&pinctrl_wdog>;
654 fsl,ext-reset-output;
655 status = "okay";
656};
657
658&iomuxc {
659 pinctrl-names = "default";
660 pinctrl-0 = <&pinctrl_hog>;
661
662 pinctrl_hog: hoggrp {
663 fsl,pins = <
664 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
Tim Harveyb94a3812021-10-06 13:13:23 -0700[diff] [blame]665 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]666 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
667 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
668 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
669 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
670 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
671 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
672 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
673 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
674 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
675 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
676 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
677 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
678 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
679 >;
680 };
681
682 pinctrl_accel: accelgrp {
683 fsl,pins = <
684 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
685 >;
686 };
687
688 pinctrl_fec1: fec1grp {
689 fsl,pins = <
690 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
691 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
692 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
693 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
694 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
695 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
696 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
697 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
698 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
699 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
700 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
701 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
702 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
703 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
704 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
705 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
706 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
707 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
708 >;
709 };
710
711 pinctrl_gsc: gscgrp {
712 fsl,pins = <
713 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
714 >;
715 };
716
717 pinctrl_i2c1: i2c1grp {
718 fsl,pins = <
719 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
720 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
721 >;
722 };
723
724 pinctrl_i2c2: i2c2grp {
725 fsl,pins = <
726 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
727 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
728 >;
729 };
730
731 pinctrl_i2c3: i2c3grp {
732 fsl,pins = <
733 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
734 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
735 >;
736 };
737
738 pinctrl_i2c4: i2c4grp {
739 fsl,pins = <
740 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
741 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
742 >;
743 };
744
745 pinctrl_gpio_leds: gpioledgrp {
746 fsl,pins = <
747 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
748 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
749 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
750 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
751 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
752 >;
753 };
754
755 pinctrl_pmic: pmicgrp {
756 fsl,pins = <
757 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
758 >;
759 };
760
761 pinctrl_pps: ppsgrp {
762 fsl,pins = <
763 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
764 >;
765 };
766
767 pinctrl_reg_wl: regwlgrp {
768 fsl,pins = <
769 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
770 >;
771 };
772
773 pinctrl_reg_usb1: regusb1grp {
774 fsl,pins = <
775 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
776 >;
777 };
778
779 pinctrl_sai3: sai3grp {
780 fsl,pins = <
781 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
782 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
783 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
784 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
785 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
786 >;
787 };
788
789 pinctrl_spi1: spi1grp {
790 fsl,pins = <
791 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
792 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
793 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
794 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
795 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
796 >;
797 };
798
799 pinctrl_spi2: spi2grp {
800 fsl,pins = <
801 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
802 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
803 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
804 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
805 >;
806 };
807
808 pinctrl_uart1: uart1grp {
809 fsl,pins = <
810 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
811 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
812 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
813 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
814 >;
815 };
816
817 pinctrl_uart1_gpio: uart1gpiogrp {
818 fsl,pins = <
819 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
820 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
821 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
822 >;
823 };
824
825 pinctrl_uart2: uart2grp {
826 fsl,pins = <
827 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
828 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
829 >;
830 };
831
832 pinctrl_uart3_gpio: uart3_gpiogrp {
833 fsl,pins = <
834 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
835 >;
836 };
837
838 pinctrl_uart3: uart3grp {
839 fsl,pins = <
840 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
841 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
842 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
843 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
844 >;
845 };
846
847 pinctrl_uart4: uart4grp {
848 fsl,pins = <
849 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
850 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
851 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
852 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
853 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
854 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
855 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
856 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
857 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
858 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
859 >;
860 };
861
862 pinctrl_usdhc2: usdhc2grp {
863 fsl,pins = <
864 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
865 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
866 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
867 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
868 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
869 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
870 >;
871 };
872
873 pinctrl_usdhc3: usdhc3grp {
874 fsl,pins = <
875 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
876 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
877 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
878 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
879 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
880 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
881 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
882 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
883 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
884 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
885 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
886 >;
887 };
888
889 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
890 fsl,pins = <
891 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
892 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
893 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
894 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
895 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
896 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
897 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
898 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
899 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
900 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
901 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
902 >;
903 };
904
905 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
906 fsl,pins = <
907 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
908 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
909 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
910 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
911 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
912 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
913 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
914 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
915 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
916 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
917 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
918 >;
919 };
920
921 pinctrl_wdog: wdoggrp {
922 fsl,pins = <
923 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
924 >;
925 };
926};