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git01.mediatek.com / filogic / uboot / 91a851346476fe00859d3693f7dd02cc40eec27c / . / arch / arm / include / asm / arch-rockchip / sdram.h
blob: bbe425deb9f917d1459f81421976f89135aa9ca7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Simon Glass0aced102015-08-30 16:55:36 -0600[diff] [blame]2/*
3 * Copyright (c) 2015 Google, Inc
4 *
5 * Copyright 2014 Rockchip Inc.
Simon Glass0aced102015-08-30 16:55:36 -0600[diff] [blame]6 */
7
8#ifndef _ASM_ARCH_RK3288_SDRAM_H__
9#define _ASM_ARCH_RK3288_SDRAM_H__
10
11enum {
12 DDR3 = 3,
13 LPDDR3 = 6,
14 UNUSED = 0xFF,
15};
16
17struct rk3288_sdram_channel {
Kever Yangcdcb91c2016-10-07 17:47:58 +0800[diff] [blame]18 /*
19 * bit width in address, eg:
20 * 8 banks using 3 bit to address,
21 * 2 cs using 1 bit to address.
22 */
Simon Glass0aced102015-08-30 16:55:36 -0600[diff] [blame]23 u8 rank;
24 u8 col;
25 u8 bk;
26 u8 bw;
27 u8 dbw;
28 u8 row_3_4;
29 u8 cs0_row;
30 u8 cs1_row;
Xu Ziyuanb0459bd2016-08-12 15:43:48 +0800[diff] [blame]31#if CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass19d66912016-07-04 11:58:25 -0600[diff] [blame]32 /*
33 * For of-platdata, which would otherwise convert this into two
34 * byte-swapped integers. With a size of 9 bytes, this struct will
35 * appear in of-platdata as a byte array.
Xu Ziyuanb0459bd2016-08-12 15:43:48 +0800[diff] [blame]36 *
37 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
Simon Glass19d66912016-07-04 11:58:25 -0600[diff] [blame]38 */
39 u8 dummy;
Xu Ziyuanb0459bd2016-08-12 15:43:48 +0800[diff] [blame]40#endif
Simon Glass0aced102015-08-30 16:55:36 -0600[diff] [blame]41};
42
43struct rk3288_sdram_pctl_timing {
44 u32 togcnt1u;
45 u32 tinit;
46 u32 trsth;
47 u32 togcnt100n;
48 u32 trefi;
49 u32 tmrd;
50 u32 trfc;
51 u32 trp;
52 u32 trtw;
53 u32 tal;
54 u32 tcl;
55 u32 tcwl;
56 u32 tras;
57 u32 trc;
58 u32 trcd;
59 u32 trrd;
60 u32 trtp;
61 u32 twr;
62 u32 twtr;
63 u32 texsr;
64 u32 txp;
65 u32 txpdll;
66 u32 tzqcs;
67 u32 tzqcsi;
68 u32 tdqs;
69 u32 tcksre;
70 u32 tcksrx;
71 u32 tcke;
72 u32 tmod;
73 u32 trstl;
74 u32 tzqcl;
75 u32 tmrr;
76 u32 tckesr;
77 u32 tdpd;
78};
79check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
80
81struct rk3288_sdram_phy_timing {
82 u32 dtpr0;
83 u32 dtpr1;
84 u32 dtpr2;
85 u32 mr[4];
86};
87
88struct rk3288_base_params {
89 u32 noc_timing;
90 u32 noc_activate;
91 u32 ddrconfig;
92 u32 ddr_freq;
93 u32 dramtype;
Kever Yangcdcb91c2016-10-07 17:47:58 +0800[diff] [blame]94 /*
95 * DDR Stride is address mapping for DRAM space
96 * Stride Ch 0 range Ch1 range Total
97 * 0x00 0-256MB 256MB-512MB 512MB
98 * 0x05 0-1GB 0-1GB 1GB
99 * 0x09 0-2GB 0-2GB 2GB
100 * 0x0d 0-4GB 0-4GB 4GB
101 * 0x17 N/A 0-4GB 4GB
102 * 0x1a 0-4GB 4GB-8GB 8GB
103 */
Simon Glass0aced102015-08-30 16:55:36 -0600[diff] [blame]104 u32 stride;
105 u32 odt;
106};
107
Simon Glass0aced102015-08-30 16:55:36 -0600[diff] [blame]108#endif