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Jan Kiszkaddf21d52020-06-23 13:15:08 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) Siemens AG, 2020
4 *
5 * Authors:
6 * Jan Kiszka <jan.kiszka@siemens.com>
7 *
8 * Derived from linux/drivers/watchdog/rti_wdt.c
9 */
10
Jan Kiszkaddf21d52020-06-23 13:15:08 +020011#include <clk.h>
12#include <dm.h>
Jan Kiszkad35cdfb2021-09-18 08:17:55 +020013#include <dm/device_compat.h>
Jan Kiszkaddf21d52020-06-23 13:15:08 +020014#include <power-domain.h>
15#include <wdt.h>
16#include <asm/io.h>
Jan Kiszkad35cdfb2021-09-18 08:17:55 +020017#include <remoteproc.h>
Jan Kiszkaddf21d52020-06-23 13:15:08 +020018
19/* Timer register set definition */
20#define RTIDWDCTRL 0x90
21#define RTIDWDPRLD 0x94
22#define RTIWDSTATUS 0x98
23#define RTIWDKEY 0x9c
24#define RTIDWDCNTR 0xa0
25#define RTIWWDRXCTRL 0xa4
26#define RTIWWDSIZECTRL 0xa8
27
28#define RTIWWDRX_NMI 0xa
29
30#define RTIWWDSIZE_50P 0x50
31
32#define WDENABLE_KEY 0xa98559da
33
34#define WDKEY_SEQ0 0xe51a
35#define WDKEY_SEQ1 0xa35c
36
37#define WDT_PRELOAD_SHIFT 13
38
39#define WDT_PRELOAD_MAX 0xfff
40
41struct rti_wdt_priv {
42 phys_addr_t regs;
Jan Kiszka7c48f892022-03-08 07:25:50 +010043 unsigned int clk_hz;
Jan Kiszkaddf21d52020-06-23 13:15:08 +020044};
45
Jan Kiszkad35cdfb2021-09-18 08:17:55 +020046#ifdef CONFIG_WDT_K3_RTI_LOAD_FW
47#define RTI_WDT_FIT_PATH "/fit-images/k3-rti-wdt-firmware"
48
49static int rti_wdt_load_fw(struct udevice *dev)
50{
51 struct udevice *rproc_dev;
52 int primary_core, ret;
53 u32 cluster_mode;
54 ofnode node;
55 u64 rti_wdt_fw;
56 u32 rti_wdt_fw_size;
57
58 node = ofnode_path(RTI_WDT_FIT_PATH);
59 if (!ofnode_valid(node))
60 goto fit_error;
61
62 ret = ofnode_read_u64(node, "load", &rti_wdt_fw);
63 if (ret)
64 goto fit_error;
65 ret = ofnode_read_u32(node, "size", &rti_wdt_fw_size);
66 if (ret)
67 goto fit_error;
68
69 node = ofnode_by_compatible(ofnode_null(), "ti,am654-r5fss");
70 if (!ofnode_valid(node))
71 goto dt_error;
72
73 ret = ofnode_read_u32(node, "ti,cluster-mode", &cluster_mode);
74 if (ret)
75 cluster_mode = 1;
76
77 node = ofnode_by_compatible(node, "ti,am654-r5f");
78 if (!ofnode_valid(node))
79 goto dt_error;
80
81 ret = uclass_get_device_by_ofnode(UCLASS_REMOTEPROC, node, &rproc_dev);
82 if (ret)
83 return ret;
84
85 primary_core = dev_seq(rproc_dev);
86
87 ret = rproc_dev_init(primary_core);
88 if (ret)
89 goto fw_error;
90
91 if (cluster_mode == 1) {
92 ret = rproc_dev_init(primary_core + 1);
93 if (ret)
94 goto fw_error;
95 }
96
97 ret = rproc_load(primary_core, (ulong)rti_wdt_fw,
98 rti_wdt_fw_size);
99 if (ret)
100 goto fw_error;
101
102 ret = rproc_start(primary_core);
103 if (ret)
104 goto fw_error;
105
106 return 0;
107
108fit_error:
109 dev_err(dev, "No loadable firmware found under %s\n", RTI_WDT_FIT_PATH);
110 return -ENOENT;
111
112dt_error:
113 dev_err(dev, "No compatible firmware target processor found\n");
114 return -ENODEV;
115
116fw_error:
117 dev_err(dev, "Failed to load watchdog firmware into remote processor %d\n",
118 primary_core);
119 return ret;
120}
121#else
122static inline int rti_wdt_load_fw(struct udevice *dev)
123{
124 return 0;
125}
126#endif
127
Jan Kiszkaddf21d52020-06-23 13:15:08 +0200128static int rti_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
129{
130 struct rti_wdt_priv *priv = dev_get_priv(dev);
131 u32 timer_margin;
132 int ret;
133
Alexander Sverdlin9178ab92024-11-08 22:15:03 +0100134 timer_margin = timeout_ms * priv->clk_hz / 1000;
135 timer_margin >>= WDT_PRELOAD_SHIFT;
136 if (timer_margin > WDT_PRELOAD_MAX)
137 timer_margin = WDT_PRELOAD_MAX;
138
139 if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY &&
140 readl(priv->regs + RTIDWDPRLD) != timer_margin)
Jan Kiszkaddf21d52020-06-23 13:15:08 +0200141 return -EBUSY;
142
Jan Kiszkad35cdfb2021-09-18 08:17:55 +0200143 ret = rti_wdt_load_fw(dev);
144 if (ret < 0)
145 return ret;
146
Jan Kiszkaddf21d52020-06-23 13:15:08 +0200147 writel(timer_margin, priv->regs + RTIDWDPRLD);
148 writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL);
149 writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL);
150
151 readl(priv->regs + RTIWWDSIZECTRL);
152
153 writel(WDENABLE_KEY, priv->regs + RTIDWDCTRL);
154
155 return 0;
156}
157
158static int rti_wdt_reset(struct udevice *dev)
159{
160 struct rti_wdt_priv *priv = dev_get_priv(dev);
161 u32 prld;
162
163 /* Make sure we do not reset too early */
164 prld = readl(priv->regs + RTIDWDPRLD) << WDT_PRELOAD_SHIFT;
165 if (readl(priv->regs + RTIDWDCNTR) >= prld / 2)
166 return -EPERM;
167
168 writel(WDKEY_SEQ0, priv->regs + RTIWDKEY);
169 writel(WDKEY_SEQ1, priv->regs + RTIWDKEY);
170
171 return 0;
172}
173
174static int rti_wdt_probe(struct udevice *dev)
175{
176 struct rti_wdt_priv *priv = dev_get_priv(dev);
177 struct clk clk;
178 int ret;
179
180 priv->regs = devfdt_get_addr(dev);
181 if (!priv->regs)
182 return -EINVAL;
183
184 ret = clk_get_by_index(dev, 0, &clk);
185 if (ret)
186 return ret;
187
Jan Kiszka7c48f892022-03-08 07:25:50 +0100188 priv->clk_hz = clk_get_rate(&clk);
189
190 /*
191 * If watchdog is running at 32k clock, it is not accurate.
192 * Adjust frequency down in this case so that it does not expire
193 * earlier than expected.
194 */
195 if (priv->clk_hz < 32768)
196 priv->clk_hz = priv->clk_hz * 9 / 10;
Jan Kiszkaddf21d52020-06-23 13:15:08 +0200197
198 return 0;
199}
200
201static const struct wdt_ops rti_wdt_ops = {
202 .start = rti_wdt_start,
203 .reset = rti_wdt_reset,
204};
205
206static const struct udevice_id rti_wdt_ids[] = {
207 { .compatible = "ti,j7-rti-wdt" },
208 { }
209};
210
211U_BOOT_DRIVER(rti_wdt) = {
212 .name = "rti_wdt",
213 .id = UCLASS_WDT,
214 .of_match = rti_wdt_ids,
215 .ops = &rti_wdt_ops,
216 .probe = rti_wdt_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700217 .priv_auto = sizeof(struct rti_wdt_priv),
Simon Glass12810652021-01-24 14:32:42 -0700218 .flags = DM_FLAG_LEAVE_PD_ON,
Jan Kiszkaddf21d52020-06-23 13:15:08 +0200219};