Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Christophe Leroy | 3598295 | 2017-07-07 10:16:42 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2010-2017 CS Systemes d'Information |
| 4 | * Florent Trinh Thai <florent.trinh-thai@c-s.fr> |
| 5 | * Christophe Leroy <christophe.leroy@c-s.fr> |
Christophe Leroy | 3598295 | 2017-07-07 10:16:42 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <config.h> |
| 9 | #include <common.h> |
| 10 | #include <nand.h> |
Tom Rini | 3bde7e2 | 2021-09-22 14:50:35 -0400 | [diff] [blame] | 11 | #include <linux/mtd/rawnand.h> |
Christophe Leroy | 3598295 | 2017-07-07 10:16:42 +0200 | [diff] [blame] | 12 | #include <asm/io.h> |
| 13 | |
| 14 | #define BIT_CLE ((unsigned short)0x0800) |
| 15 | #define BIT_ALE ((unsigned short)0x0400) |
| 16 | #define BIT_NCE ((unsigned short)0x1000) |
| 17 | |
| 18 | static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) |
| 19 | { |
Christophe Leroy | a1868ae | 2018-03-16 17:20:49 +0100 | [diff] [blame] | 20 | struct nand_chip *this = mtd_to_nand(mtdinfo); |
Christophe Leroy | 3598295 | 2017-07-07 10:16:42 +0200 | [diff] [blame] | 21 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 22 | unsigned short pddat = 0; |
| 23 | |
| 24 | /* The hardware control change */ |
| 25 | if (ctrl & NAND_CTRL_CHANGE) { |
| 26 | pddat = in_be16(&immr->im_ioport.iop_pddat); |
| 27 | |
| 28 | /* Clearing ALE and CLE */ |
| 29 | pddat &= ~(BIT_CLE | BIT_ALE); |
| 30 | |
| 31 | /* Driving NCE pin */ |
| 32 | if (ctrl & NAND_NCE) |
| 33 | pddat &= ~BIT_NCE; |
| 34 | else |
| 35 | pddat |= BIT_NCE; |
| 36 | |
| 37 | /* Driving CLE and ALE pin */ |
| 38 | if (ctrl & NAND_CLE) |
| 39 | pddat |= BIT_CLE; |
| 40 | if (ctrl & NAND_ALE) |
| 41 | pddat |= BIT_ALE; |
| 42 | |
| 43 | out_be16(&immr->im_ioport.iop_pddat, pddat); |
| 44 | } |
| 45 | |
| 46 | /* Writing the command */ |
| 47 | if (cmd != NAND_CMD_NONE) |
| 48 | out_8(this->IO_ADDR_W, cmd); |
| 49 | } |
| 50 | |
| 51 | int board_nand_init(struct nand_chip *nand) |
| 52 | { |
| 53 | immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; |
| 54 | |
| 55 | /* Set GPIO Port */ |
| 56 | setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00); |
| 57 | clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00); |
| 58 | clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000); |
| 59 | |
| 60 | nand->chip_delay = 60; |
| 61 | nand->ecc.mode = NAND_ECC_SOFT; |
| 62 | nand->cmd_ctrl = nand_hwcontrol; |
| 63 | |
| 64 | return 0; |
| 65 | } |