Blame - board/dbau1x00/memsetup.S - filogic/uboot

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wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	1	/* Memory sub-system initialization code */
				2
				3	#include <config.h>
				4	#include <version.h>
				5	#include <asm/regdef.h>
				6	#include <asm/au1x00.h>
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	7	#include <asm/mipsregs.h>
				8
				9	#define AU1500_SYS_ADDR 0xB1900000
				10	#define sys_endian 0x0038
				11	#define CP0_Config0 $16
				12	#define MEM_1MS ((396000000/1000000) * 1000)
				13
				14	.text
				15	.set noreorder
				16	.set mips32
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	17
				18	.globl memsetup
				19	memsetup:
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	20	/*
				21	* Step 1) Establish CPU endian mode.
				22	* Db1500-specific:
				23	* Switch S1.1 Off(bit7 reads 1) is Little Endian
				24	* Switch S1.1 On (bit7 reads 0) is Big Endian
				25	*/
				26	li t0, MEM_STCFG1
				27	li t1, 0x00000080
				28	sw t1, 0(t0)
				29
				30	li t0, MEM_STTIME1
				31	li t1, 0x22080a20
				32	sw t1, 0(t0)
				33
				34	li t0, MEM_STADDR1
				35	li t1, 0x10c03f00
				36	sw t1, 0(t0)
				37
				38	li t0, 0xAE000008
				39	lw t1,0(t0)
				40	andi t1,t1,0x80
				41	beq zero,t1,big_endian
				42	nop
				43	little_endian:
				44
				45	/* Change Au1 core to little endian */
				46	li t0, AU1500_SYS_ADDR
				47	li t1, 1
				48	sw t1, sys_endian(t0)
				49	mfc0 t2, CP0_CONFIG
				50	mtc0 t2, CP0_CONFIG
				51	nop
				52	nop
				53
				54	/* Big Endian is default so nothing to do but fall through */
				55
				56	big_endian:
				57
				58	/*
				59	* Step 2) Establish Status Register
				60	* (set BEV, clear ERL, clear EXL, clear IE)
				61	*/
				62	li t1, 0x00400000
				63	mtc0 t1, CP0_STATUS
				64
				65	/*
				66	* Step 3) Establish CP0 Config0
				67	* (set OD, set K0=3)
				68	*/
				69	li t1, 0x00080003
				70	mtc0 t1, CP0_CONFIG
				71
				72	/*
				73	* Step 4) Disable Watchpoint facilities
				74	*/
				75	li t1, 0x00000000
				76	mtc0 t1, CP0_WATCHLO
				77	mtc0 t1, CP0_IWATCHLO
				78	/*
				79	* Step 5) Disable the performance counters
				80	*/
				81	mtc0 zero, CP0_PERFORMANCE
				82	nop
				83
				84	/*
				85	* Step 6) Establish EJTAG Debug register
				86	*/
				87	mtc0 zero, CP0_DEBUG
				88	nop
				89
				90	/*
				91	* Step 7) Establish Cause
				92	* (set IV bit)
				93	*/
				94	li t1, 0x00800000
				95	mtc0 t1, CP0_CAUSE
				96
				97	/* Establish Wired (and Random) */
				98	mtc0 zero, CP0_WIRED
				99	nop
				100
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	101	/* First setup pll:s to make serial work ok */
				102	/* We have a 12 MHz crystal */
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	103	li t0, SYS_CPUPLL
				104	li t1, 0x21 /* 396 MHz */
				105	sw t1, 0(t0)
wdenk	9c53f40	2003-10-15 23:53:47 +0000	[diff] [blame]	106	sync
				107	nop
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	108	nop
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	109
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	110	/* wait 1mS for clocks to settle */
				111	li t1, MEM_1MS
				112	1: add t1, -1
				113	bne t1, zero, 1b
				114	nop
wdenk	9c53f40	2003-10-15 23:53:47 +0000	[diff] [blame]	115	/* Setup AUX PLL */
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	116	li t0, SYS_AUXPLL
				117	li t1, 0x20 /* 96 MHz */
				118	sw t1, 0(t0) /* aux pll */
wdenk	9c53f40	2003-10-15 23:53:47 +0000	[diff] [blame]	119	sync
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	120
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	121	/* Static memory controller */
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	122
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	123	/* RCE0 AMD 29LV640M MirrorBit Flash */
				124	li t0, MEM_STCFG0
				125	li t1, 0x00000013
				126	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	127
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	128	li t0, MEM_STTIME0
				129	li t1, 0x040181D7
				130	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	131
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	132	li t0, MEM_STADDR0
				133	li t1, 0x11E03F80
				134	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	135
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	136	/* RCE1 CPLD Board Logic */
				137	li t0, MEM_STCFG1
				138	li t1, 0x00000080
				139	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	140
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	141	li t0, MEM_STTIME1
				142	li t1, 0x22080a20
				143	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	144
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	145	li t0, MEM_STADDR1
				146	li t1, 0x10c03f00
				147	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	148
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	149	/* RCE2 CPLD Board Logic */
				150	li t0, MEM_STCFG2
				151	li t1, 0x00000000
				152	sw t1, 0(t0)
				153
				154	li t0, MEM_STTIME2
				155	li t1, 0x00000000
				156	sw t1, 0(t0)
				157
				158	li t0, MEM_STADDR2
				159	li t1, 0x00000000
				160	sw t1, 0(t0)
				161
				162	/* RCE3 PCMCIA 250ns */
				163	li t0, MEM_STCFG3
				164	li t1, 0x00000002
				165	sw t1, 0(t0)
				166
				167	li t0, MEM_STTIME3
				168	li t1, 0x280E3E07
				169	sw t1, 0(t0)
				170
				171	li t0, MEM_STADDR3
				172	li t1, 0x10000000
				173	sw t1, 0(t0)
				174
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	175	sync
				176
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	177	/* Set peripherals to a known state */
				178	li t0, IC0_CFG0CLR
				179	li t1, 0xFFFFFFFF
				180	sw t1, 0(t0)
				181
				182	li t0, IC0_CFG0CLR
				183	sw t1, 0(t0)
				184
				185	li t0, IC0_CFG1CLR
				186	sw t1, 0(t0)
				187
				188	li t0, IC0_CFG2CLR
				189	sw t1, 0(t0)
				190
				191	li t0, IC0_SRCSET
				192	sw t1, 0(t0)
				193
				194	li t0, IC0_ASSIGNSET
				195	sw t1, 0(t0)
				196
				197	li t0, IC0_WAKECLR
				198	sw t1, 0(t0)
				199
				200	li t0, IC0_RISINGCLR
				201	sw t1, 0(t0)
				202
				203	li t0, IC0_FALLINGCLR
				204	sw t1, 0(t0)
				205
				206	li t0, IC0_TESTBIT
				207	li t1, 0x00000000
				208	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	209	sync
				210
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	211	li t0, IC1_CFG0CLR
				212	li t1, 0xFFFFFFFF
				213	sw t1, 0(t0)
				214
				215	li t0, IC1_CFG0CLR
				216	sw t1, 0(t0)
				217
				218	li t0, IC1_CFG1CLR
				219	sw t1, 0(t0)
				220
				221	li t0, IC1_CFG2CLR
				222	sw t1, 0(t0)
				223
				224	li t0, IC1_SRCSET
				225	sw t1, 0(t0)
				226
				227	li t0, IC1_ASSIGNSET
				228	sw t1, 0(t0)
				229
				230	li t0, IC1_WAKECLR
				231	sw t1, 0(t0)
				232
				233	li t0, IC1_RISINGCLR
				234	sw t1, 0(t0)
				235
				236	li t0, IC1_FALLINGCLR
				237	sw t1, 0(t0)
				238
				239	li t0, IC1_TESTBIT
				240	li t1, 0x00000000
				241	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	242	sync
				243
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	244	li t0, SYS_FREQCTRL0
				245	li t1, 0x00000000
				246	sw t1, 0(t0)
				247
				248	li t0, SYS_FREQCTRL1
				249	li t1, 0x00000000
				250	sw t1, 0(t0)
				251
				252	li t0, SYS_CLKSRC
				253	li t1, 0x00000000
				254	sw t1, 0(t0)
				255
				256	li t0, SYS_PININPUTEN
				257	li t1, 0x00000000
				258	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	259	sync
				260
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	261	li t0, 0xB1100100
				262	li t1, 0x00000000
				263	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	264
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	265	li t0, 0xB1400100
				266	li t1, 0x00000000
				267	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	268
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	269
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	270	li t0, SYS_WAKEMSK
				271	li t1, 0x00000000
				272	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	273
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	274	li t0, SYS_WAKESRC
				275	li t1, 0x00000000
				276	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	277
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	278	/* wait 1mS before setup */
				279	li t1, MEM_1MS
				280	1: add t1, -1
				281	bne t1, zero, 1b
				282	nop
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	283
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	284	/* SDCS 0,1 SDRAM */
				285	li t0, MEM_SDMODE0
				286	li t1, 0x005522AA
				287	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	288
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	289	li t0, MEM_SDMODE1
				290	li t1, 0x005522AA
				291	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	292
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	293	li t0, MEM_SDMODE2
				294	li t1, 0x00000000
				295	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	296
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	297	li t0, MEM_SDADDR0
				298	li t1, 0x001003F8
				299	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	300
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	301
				302	li t0, MEM_SDADDR1
				303	li t1, 0x001023F8
				304	sw t1, 0(t0)
				305
				306	li t0, MEM_SDADDR2
				307	li t1, 0x00000000
				308	sw t1, 0(t0)
				309
				310	sync
				311
				312	li t0, MEM_SDREFCFG
				313	li t1, 0x64000C24 /* Disable */
				314	sw t1, 0(t0)
				315	sync
				316
				317	li t0, MEM_SDPRECMD
				318	sw zero, 0(t0)
				319	sync
				320
				321	li t0, MEM_SDAUTOREF
				322	sw zero, 0(t0)
				323	sync
				324	sw zero, 0(t0)
				325	sync
				326
				327	li t0, MEM_SDREFCFG
				328	li t1, 0x66000C24 /* Enable */
				329	sw t1, 0(t0)
				330	sync
				331
				332	li t0, MEM_SDWRMD0
				333	li t1, 0x00000033
				334	sw t1, 0(t0)
				335	sync
				336
				337	li t0, MEM_SDWRMD1
				338	li t1, 0x00000033
				339	sw t1, 0(t0)
				340	sync
				341
				342	/* wait 1mS after setup */
				343	li t1, MEM_1MS
				344	1: add t1, -1
				345	bne t1, zero, 1b
				346	nop
				347
				348	li t0, SYS_PINFUNC
				349	li t1, 0x00008080
				350	sw t1, 0(t0)
				351
				352	li t0, SYS_TRIOUTCLR
				353	li t1, 0x00001FFF
				354	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	355
wdenk	0260cd6	2004-01-02 15:01:32 +0000	[diff] [blame]	356	li t0, SYS_OUTPUTCLR
				357	li t1, 0x00008000
				358	sw t1, 0(t0)
wdenk	9b7f384	2003-10-09 20:09:04 +0000	[diff] [blame]	359	sync
				360
				361	j ra
				362	nop